Patents by Inventor Mehran Sedigh

Mehran Sedigh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7981800
    Abstract: A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness. Generally, the method involves depositing a nitride over pad oxide on a substrate using plasma enhanced chemical vapor deposition (PECVD), and patterning the PECVD nitride to form a field oxide mask. In certain embodiments, patterning the PECVD nitride involves: (i) forming a patterned resist layer on the PECVD nitride; (ii) etching in a process chamber at least one opening through at least the PECVD nitride; and (iii) stripping the patterned resist layer in-situ in the same process chamber in which the at least one opening was etched through the PECVD nitride using a fluorine based plasma. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: July 19, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Geethakrishnan Narasimhan, Mehran Sedigh
  • Patent number: 7446063
    Abstract: A method of forming structures comprises depositing silicon nitride films simultaneously on a plurality of substrates at a first temperature, and heating the silicon nitride films at a temperature greater than the first temperature.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: November 4, 2008
    Assignee: Cypress Semiconductor Corp.
    Inventors: Sagy Levy, Mehran Sedigh
  • Patent number: 7323377
    Abstract: In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: January 29, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mehran Sedigh, Manuj Rathor, Alain P. Blosse, Dutta Saurabh Chowdhury
  • Patent number: 7078334
    Abstract: According to one embodiment, a method (100) may include forming a first insulating layer over a semiconductor substrate (step 102), forming a hard mask layer (step 104), and forming a photoresist etch mask having a thickness of less than about 4,000 angstroms (step 106). Such a reduced thickness may conventionally lead to uncontrolled etching and/or may require multiple steps to ensure feature formation. A method (100) may further include etching an opening through at least one half the thickness of the hard mask layer to form a hard mask (step 108) and etching through a first insulating layer without first removing a photoresist layer (step 110). Such etching can essentially consume a photoresist layer, however controllability can be maintained as etching may continue with a hard mask in place.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: July 18, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Saurabh Dutta Chowdhury, Mehran Sedigh, Chan Lon Yang, Prabhu Goplana
  • Patent number: 6893974
    Abstract: A system and method is provided herein to fabricate openings in a semiconductor topography using feed forward control of etch process parameters. In one embodiment, a method includes measuring one or more dimensional features of a semiconductor topography to obtain pre-etch values. The method also includes determining a statistical result of the pre-etch values and adjusting one or more processing parameters if the statistical result is less than a target value. Subsequently, the method includes etching the semiconductor topography based upon the statistical result to form one or more openings in the semiconductor topography. As such, the system and method described herein fabricates openings using feed forward control of the etch process parameters to compensate for structural variations within semiconductor topographies that may exist between wafer-to-wafer and/or between lot-to-lot.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: May 17, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Mehran Sedigh, Saurabu Dutta Chowdhury
  • Patent number: 6866986
    Abstract: A method of forming a photoresist includes forming a photoresist and patterning/developing it according to conventional methods. The photoresist is then subjected to ion implantation. The ions may be selected from the group consisting of argon, boron, boron fluoride, arsenic, phosphorous and nitrogen. The ion implantation during processing of the photoresist provides a stabilized photoresist and helps reduce CD loss, loss of the photoresist and formation of pin holes and striations.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: March 15, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jun Sung Chun, Mehran Sedigh, Christ Ford
  • Publication number: 20040009437
    Abstract: A method of forming a photoresist includes forming a photoresist and patterning/developing it according to conventional methods. The photoresist is then subjected to ion implantation. The ions may be selected from the group consisting of argon, boron, boron fluoride, arsenic, phosphorous and nitrogen. The ion implantation during processing of the photoresist provides a stabilized photoresist and helps reduce CD loss, loss of the photoresist and formation of pin holes and striations.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 15, 2004
    Inventors: Jun Sung Chun, Mehran Sedigh, Christ Ford