Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: Systems and methods to detect seizures using analog circuitry. One example method generally includes obtaining, at a seizure detection system, one or more electroencephalogram (EEG) signals, detecting a plurality of features associated with each of the one or more EEG signals, generating a bitstream indicating a seizure probability associated with each feature of the plurality of features to yield a plurality of bitstreams indicating a plurality of seizure probabilities, and generating a seizure detection output based on the plurality of bitstreams indicating the plurality of seizure probabilities of the plurality of features.

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: A system and method for separating a venous component and an arterial component from a red signal and an infrared signal of a PPG sensor is provided. The method uses the second order statistics of venous and arterial signals to separate the venous and arterial signals. After reliable separation of the venous and the arterial component signals, the component signals can be used for different purposes. In a preferred embodiment, the respiratory signal, pattern, and rate are extracted from the separated venous component and a reliable “ratio of ratios” is extracted for SpO2 using only the arterial component of the PPG signals. The disclosed embodiments enable real-time continuous monitoring of respiration pattern/rate and site-independent arterial oxygen saturation.

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: A system and method for signal processing to remove unwanted noise components including: (i) wavelength-independent motion artifacts such as tissue, bone and skin effects, and (ii) wavelength-dependent motion artifact/noise components such as venous blood pulsation and movement due to various sources including muscle pump, respiratory pump and physical perturbation. Disclosed are methods, analytics, and their uses for reliable perfusion monitoring, arterial oxygen saturation monitoring, heart rate monitoring during daily activities and in hospital settings and for extraction of physiological parameters such as respiration information, hemodynamic parameters, venous capacity, and fluid responsiveness. The system and methods disclosed are extendable to include monitoring platforms for perfusion, hypoxia, arrhythmia detection, airway obstruction detection and sleep disorders including apnea.

Abstract: The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: With the increasing demand for improved processor performance, memory systems have been growing increasingly larger to keep up with this performance demand. Caches, which dictate the performance of memory systems are often the focus of improved performance in memory systems, and the most common techniques used to increase cache performance are increased size and associativity. Unfortunately, these methods yield increased static and dynamic power consumption. In this invention, a technique is shown that reduces the power consumption in associative caches with some improvement in cache performance. The architecture shown achieves these power savings by reducing the number of ways queried on each cache access, using a simple hash function and no additional storage, while skipping some pipe stages for improved performance. Up to 90% reduction in power consumption with a 4.6% performance improvement was observed.

Abstract: The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: With the increasing demand for improved processor performance, memory systems have been growing increasingly larger to keep up with this performance demand. Caches, which dictate the performance of memory systems are often the focus of improved performance in memory systems, and the most common techniques used to increase cache performance are increased size and associativity. Unfortunately, these methods yield increased static and dynamic power consumption. In this invention, a technique is shown that reduces the power consumption in associative caches with some improvement in cache performance. The architecture shown achieves these power savings by reducing the number of ways queried on each cache access, using a simple hash function and no additional storage, while skipping some pipe stages for improved performance. Up to 90% reduction in power consumption with a 4.6% performance improvement was observed.

Abstract: A device and method for heart performance characterization and abnormality detection is disclosed herein. The device and method analyze and characterize cardiac electrophysiological signals which help in the diagnosis of myocardial ischemia in advance of a heart attack.

Abstract: A system and method for separating a venous component and an arterial component from a red signal and an infrared signal of a PPG sensor is provided. The method uses the second order statistics of venous and arterial signals to separate the venous and arterial signals. After reliable separation of the venous and the arterial component signals, the component signals can be used for different purposes. In a preferred embodiment, the respiratory signal, pattern, and rate are extracted from the separated venous component and a reliable “ratio of ratios” is extracted for SpO2 using only the arterial component of the PPG signals. The disclosed embodiments enable real-time continuous monitoring of respiration pattern/rate and site-independent arterial oxygen saturation.

Abstract: A system and method for signal processing to remove unwanted noise components including: (i) wavelength-independent motion artifacts such as tissue, bone and skin effects, and (ii) wavelength-dependent motion artifact/noise components such as venous blood pulsation and movement due to various sources including muscle pump, respiratory pump and physical perturbation. Disclosed are methods, analytics, and their uses for reliable perfusion monitoring, arterial oxygen saturation monitoring, heart rate monitoring during daily activities and in hospital settings and for extraction of physiological parameters such as respiration information, hemodynamic parameters, venous capacity, and fluid responsiveness. The system and methods disclosed are extendable to include monitoring platforms for perfusion, hypoxia, arrhythmia detection, airway obstruction detection and sleep disorders including apnea.