Patents by Inventor Mehrdad Ramezani
Mehrdad Ramezani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240015005Abstract: A hashing system includes data storage circuit elements that store words to be used for hashing a message. Each data storage circuit element stores a word without moving the word to any other data storage circuit element during hashing. The hashing system includes combinational logic circuit element(s) that select specified data storage circuit elements according to a specified order that simulates shifting of at least a subset of the words among the data storage circuit elements, for instance based on an order in which the words were stored and/or based a clock. The hashing system includes computational operator(s) that generate additional word(s) based on the selected specified words. The hashing system stores the additional word(s) into available data storage circuit element(s), in some cases overwriting prior word(s) that were stored in the available data storage circuit element(s). The hashing system can include a message expander (ME) and/or message compressor (MC).Type: ApplicationFiled: July 6, 2022Publication date: January 11, 2024Inventors: William Song, Yue Yang, Bertram Leesti, Mehrdad Ramezani, Afshin Rezayee, Kajornsak Julavittayanukool, Weili Chen
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Patent number: 10211972Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.Type: GrantFiled: June 21, 2017Date of Patent: February 19, 2019Assignee: Rambus Inc.Inventors: Mehrdad Ramezani, David J. Cassan, Christopher D. Holdenried, Sang-Wook Paul Park, Marcus Van Ierssel
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Publication number: 20170346618Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.Type: ApplicationFiled: June 21, 2017Publication date: November 30, 2017Inventors: Mehrdad Ramezani, David J. Cassan, Christopher D. Holdenried, Sang-Wook Paul Park, Marcus Van Ierssel
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Patent number: 9716582Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.Type: GrantFiled: September 30, 2015Date of Patent: July 25, 2017Assignee: Rambus Inc.Inventors: Mehrdad Ramezani, David J. Cassan, Christopher D. Holdenried, Sang-Wook Paul Park, Marcus van Ierssel
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Publication number: 20170093558Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Applicant: Rambus Inc.Inventors: Mehrdad Ramezani, David J. Cassan, Christopher D. Holdenried, Sang-Wook Paul Park, Marcus van Ierssel
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Patent number: 8878568Abstract: A high speed transmit driver is provided, along with methods to improve driver slew rate, decrease transmit jitter, improve termination accuracy, and decrease sensitivity to supply noise.Type: GrantFiled: October 24, 2012Date of Patent: November 4, 2014Assignee: Semtech CorporationInventors: Kamran Farzan, Mehrdad Ramezani, David Cassan, Angus McLaren, Saman Sadr
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Patent number: 8170169Abstract: A phase lockedcircuit comprising a phase detector for comparing an incoming serial data signal with a feedback clock signal and generating a digital phase detector output signal representing a phase difference between the incoming data signal and the feedback clock signal; a dual path filter for receiving the phase detector output signal, the dual path filter including a first path for generating a digital proportional output signal that is proportional to the phase detector output signal and a second path having an integral digital filter for generating a digital integral output signal that is proportional to an integral of the phase detector output signal; and a digitally controlled oscillator for receiving the proportional output signal and the integral output signal as tuning inputs and generating in dependence thereon an output clock signal from which the feedback clock signal is obtained. The circuit can be implemented in a receive path of a serializer/deserializer.Type: GrantFiled: November 30, 2007Date of Patent: May 1, 2012Assignee: Snowbush Inc.Inventors: Kenneth W. Martin, Jonathan E. Rogers, Tony Pialis, Mehrdad Ramezani
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Publication number: 20080130816Abstract: A phase lockedcircuit comprising a phase detector for comparing an incoming serial data signal with a feedback clock signal and generating a digital phase detector output signal representing a phase difference between the incoming data signal and the feedback clock signal; a dual path filter for receiving the phase detector output signal, the dual path filter including a first path for generating a digital proportional output signal that is proportional to the phase detector output signal and a second path having an integral digital filter for generating a digital integral output signal that is proportional to an integral of the phase detector output signal; and a digitally controlled oscillator for receiving the proportional output signal and the integral output signal as tuning inputs and generating in dependence thereon an output clock signal from which the feedback clock signal is obtained. The circuit can be implemented in a receive path of a serializer/deserializer.Type: ApplicationFiled: November 30, 2007Publication date: June 5, 2008Inventors: Kenneth W. Martin, Jonathan E. Rogers, Tony Pialis, Mehrdad Ramezani