Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.

Abstract: A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.

Abstract: A design verification system simulates operation of an electronic device to identify one or more power characteristic vs. temperature (PC-T) curves for the electronic device. Each of the one or more PC-T curves indicates, for a particular reliability characteristic limit, a range of power characteristic values over a corresponding range of temperatures that are not expected to result in the reliability characteristic limit being exceeded. Based on the one or more PC-T curves, the design verification system sets a range of power characteristic limits, over a corresponding range of temperatures, for the electronic device. During operation, the electronic device employs a temperature sensor to measure an ambient or device temperature, and sets its power characteristic (voltage or current) according to the measured temperature and the power characteristic limits.

Abstract: A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

Abstract: A method of making a non-volatile memory cell includes forming a plurality of discrete storage elements. A tensile dielectric layer is formed among the discrete storage elements and provides lateral tensile stress to the discrete storage elements. A gate is formed over the discrete storage elements.

Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer.

Abstract: Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

Abstract: An integrated circuit (IC) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal layers may disrupt the functionality of the IC device if the vacancies migrate to the vias interconnecting the metal layers. To mitigate vacancy migration, stressor elements are formed at the metal traces to form stress effects in the metal traces that, depending on type, either serve to repel migrating vacancies from the via contact area or to trap migrating vacancies at a portion of the metal trace displaced from the contact area. The stressor elements may be formed as stress-inducing dielectric or conductive material overlying the metal traces, or formed by inducing a stress memory effect in a portion of the metal trace itself.

Abstract: An integrated circuit (IC) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal layers may disrupt the functionality of the IC device if the vacancies migrate to the vias interconnecting the metal layers. To mitigate vacancy migration, stressor elements are formed at the metal traces to form stress effects in the metal traces that, depending on type, either serve to repel migrating vacancies from the via contact area or to trap migrating vacancies at a portion of the metal trace displaced from the contact area. The stressor elements may be formed as stress-inducing dielectric or conductive material overlying the metal traces, or formed by inducing a stress memory effect in a portion of the metal trace itself.

Abstract: A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.

Abstract: A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.

Abstract: A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer.

Abstract: A method for integrated circuit reliability aging simulation includes dividing a target time period into N stages including a first stage and a second stage; obtaining first parameter values of a reliability model for the first stage; performing a first simulation on the circuit based on the reliability model and the first parameter values to obtain first aging results; obtaining second parameter values of the reliability model for the second stage; and performing a second simulation on the circuit based on the reliability model and the second parameter values to obtain second aging results.

Abstract: An oxide-containing layer is formed directly on a semiconductor layer in an NVM region, and a first partial layer of a first material is formed over the oxide-containing layer in the NVM region. A first high-k dielectric layer is formed directly on the semiconductor layer in a logic region. A first conductive layer is formed over the first dielectric layer in the logic region. A second partial layer of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer if the cell is a floating gate cell or a select gate if the cell is a split gate cell.

Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a first layer of a material that can be used as a gate or a dummy gate. An opening is formed in the first layer in the NVM region. The opening is filled with a charge storage layer and a control gate. A select gate, which may be formed from the first layer or from a metal layer, is formed adjacent to the control gate. If it is a metal from a metal layer, the first layer is used to form a dummy gate. A metal logic gate is formed in the logic region by replacing a dummy gate.

Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.

Abstract: A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

Abstract: A method of making a semiconductor device having a substrate includes forming a first interconnect layer over the substrate, wherein a first metal portion of a first metal type is within the first interconnect layer and has a first via interface location. An interlayer dielectric is formed over the first interconnect layer. An opening in the interlayer dielectric is formed over the via interface location of the first metal portion. A second interconnect layer is formed over the interlayer dielectric. A second metal portion and a via of the first metal type is within the second interconnect layer. The via is formed in the opening to form an electrical contact between the first metal portion and the second metal portion. The via is over the first via interface location. A first implant of the first metal type is aligned to the first via interface location.

Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.