Patents by Inventor Mehul Naik
Mehul Naik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11965236Abstract: Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.Type: GrantFiled: July 15, 2019Date of Patent: April 23, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Minrui Yu, He Ren, Mehul Naik
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Patent number: 11967527Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.Type: GrantFiled: June 18, 2022Date of Patent: April 23, 2024Assignee: APPLIED MATERIALS, INC.Inventors: He Ren, Hao Jiang, Mehul Naik
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Patent number: 11955382Abstract: Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.Type: GrantFiled: December 3, 2020Date of Patent: April 9, 2024Assignee: Applied Materials, Inc.Inventors: Kevin Kashefi, Alexander Jansen, Mehul Naik, He Ren, Lu Chen, Feng Chen
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Patent number: 11908696Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.Type: GrantFiled: January 6, 2022Date of Patent: February 20, 2024Assignee: Applied Materials, Inc.Inventors: He Ren, Hao Jiang, Mehul Naik, Wenting Hou, Jianxin Lei, Chen Gong, Yong Cao
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Publication number: 20230326925Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Applicant: Applied Materials, Inc.Inventors: Andrew Anthony Cockburn, Vanessa Pena, Daniel Philippe Cellier, John Tolle, Thomas Kirschenheiter, Wei Hong, Ellie Y. Yieh, Mehul Naik, Seshadri Ramaswami
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Patent number: 11776806Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.Type: GrantFiled: May 12, 2022Date of Patent: October 3, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Xi Cen, Yakuan Yao, Yiming Lai, Kai Wu, Avgerinos V. Gelatos, David T. Or, Kevin Kashefi, Yu Lei, Lin Dong, He Ren, Yi Xu, Mehul Naik, Hao Chen, Mang-Mang Ling
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Patent number: 11749532Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.Type: GrantFiled: May 4, 2021Date of Patent: September 5, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Hao Jiang, Chi Lu, He Ren, Mehul Naik
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Publication number: 20230260825Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.Type: ApplicationFiled: February 14, 2022Publication date: August 17, 2023Inventors: He REN, Houssam LAZKANI, Raman GAIRE, Mehul NAIK, Kuan-Ting LIU
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Patent number: 11705366Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.Type: GrantFiled: June 11, 2021Date of Patent: July 18, 2023Assignee: Micromaterials LLCInventors: He Ren, Amrita B. Mullick, Regina Freed, Mehul Naik, Uday Mitra
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Publication number: 20230187276Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Inventors: Shi YOU, He REN, Naomi YOSHIDA, Nikolaos BEKIARIS, Mehul NAIK, Jay Martin SEAMONS, Jingmei LIANG, Mei-Yee SHEK
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Patent number: 11626288Abstract: Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.Type: GrantFiled: July 30, 2021Date of Patent: April 11, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Raymond Hung, Mehul Naik, Michael Haverty
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Patent number: 11615984Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.Type: GrantFiled: April 14, 2020Date of Patent: March 28, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Shi You, He Ren, Naomi Yoshida, Nikolaos Bekiaris, Mehul Naik, Martin Jay Seamons, Jingmei Liang, Mei-Yee Shek
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Publication number: 20230045689Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: Hao Jiang, Chi Lu, He Ren, Chi-I Lang, Ho-yung David Hwang, Mehul Naik
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Publication number: 20230034058Abstract: Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Raymond HUNG, Mehul NAIK, Michael HAVERTY
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Patent number: 11508617Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.Type: GrantFiled: October 24, 2019Date of Patent: November 22, 2022Assignee: Applied Materials, Inc.Inventors: Hao Jiang, Chi Lu, He Ren, Chi-I Lang, Ho-yung David Hwang, Mehul Naik
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Publication number: 20220359224Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.Type: ApplicationFiled: May 4, 2021Publication date: November 10, 2022Inventors: Hao JIANG, Chi LU, He REN, Mehul NAIK
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Publication number: 20220328352Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.Type: ApplicationFiled: June 18, 2022Publication date: October 13, 2022Applicant: Applied Materials, Inc.Inventors: He Ren, Hao Jiang, Mehul Naik
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Publication number: 20220270871Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.Type: ApplicationFiled: May 12, 2022Publication date: August 25, 2022Applicant: Applied Materials, Inc.Inventors: Xi Cen, Yakuan Yao, Yiming Lai, Kai Wu, Avgerinos V. Gelatos, David T. Or, Kevin Kashefi, Yu Lei, Lin Dong, He Ren, Yi Xu, Mehul Naik, Hao Chen, Mang-Mang Ling
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Patent number: 11410885Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.Type: GrantFiled: May 1, 2020Date of Patent: August 9, 2022Assignee: APPLIED MATERIALS, INC.Inventors: He Ren, Hao Jiang, Mehul Naik
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Patent number: 11380536Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.Type: GrantFiled: May 5, 2020Date of Patent: July 5, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Xi Cen, Yakuan Yao, Yiming Lai, Kai Wu, Avgerinos V. Gelatos, David T. Or, Kevin Kashefi, Yu Lei, Lin Dong, He Ren, Yi Xu, Mehul Naik, Hao Chen, Mang-Mang Ling