Abstract: A device for installing curtain gliders is revealed. The device for installing curtain gliders is a positioning strip. A plurality of gliders are arranged at the positioning strip and then carried and mounted into a curtain track by the positioning strip. The positioning strip is provided with a plurality of mounting and positioning units each of which includes a main hole, two slots disposed on two ends of the main hole, and two locking pieces located between the two slots and the main hole. Thereby the glider with different designs can be inserted into the main hole and the locking pieces are abutting against the glider for positioning the glider. Installers can assemble the gliders quickly and conveniently by count marks on the positioning strip.

Abstract: Systems and methods of making a glove pack and for removing gloves from the glove pack are disclosed. The glove pack includes a stack of gloves. The stack of gloves includes a first glove engaging a second glove. The first and second gloves each have an exterior gripping surface. Each exterior gripping surface of the first and second gloves engages and adheres to the exterior gripping surface of the other of the first or second glove in the stack of gloves thereby adhering the first and second gloves together in the stack of gloves such that when the first glove is removed from the stack of gloves at least a portion of the second glove moves with the first glove.

Abstract: A semiconductor device includes an analog voltage regulator and an integrated circuit module. The analog voltage regulator generates a regulated output voltage. The integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (DVOC). The first sensor generates a digital reference voltage based on an analog reference voltage. The second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. The DVOC generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. The regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.

Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation.

Abstract: A localized heating device includes a plasma deforming portion and a heating portion. The plasma deforming portion includes an inlet end having a circular hole, an outlet end having an elongated hole with a first length and a first width, and a channel smoothly connected with the circular hole and the elongated hole. The heating portion, disposed at the outlet end, includes two control covers spaced by a slot. The elongated hole and the slot being oppositely disposed with respect to the plasma deforming portion. A plasma flow provided by a plasma producing source being to enter the channel via the circular hole, then to flow through the elongated hole, and finally to reach the slot.

Abstract: An electrical connector includes a signal joint and a circuit board seat. The circuit board seat includes a seat body, a clamp component and a mount component. The seat body includes a base portion, a mount portion and a clamp portion. The base portion is fixed to the signal joint, the mount portion and the clamp portion are respectively connected to two opposite sides of the base portion, and the base portion, the mount portion and the clamp portion together form an accommodation recess. The clamp component is movably located in the accommodation recess. The clamp component and the clamp portion together form an installation space, and the installation space is configured to accommodate a circuit board. The mount component is movably disposed through the mount portion of the seat body of the circuit board seat, and the mount component is connected to the clamp component.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.

Abstract: The disclosure relates to a motor device including a bracket, a connection assembly, a sensor, a stator and a rotor. The bracket includes a first end, a second end, a communication aperture and a slot. The communication aperture passes through the first end and the second end. The slot is disposed at the first end. The connection assembly is disposed in the slot and includes a first connector and a second connector. The second connector is inserted into an accommodation opening of the first connector. The sensor is disposed at the first end and includes a first circuit board connected to the first connector through a first connection element. The stator is connected to the second end and includes a second circuit board connected to the second connector through the second connection element. An end portion of the rotor passes through the communication aperture and spatially corresponds to the sensor.

Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.

Abstract: A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.

Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: A voltage regulator includes an output node, a control circuit, and a power stage. The control circuit is configured to receive a power state signal from a load circuit coupled to the output node, and output a control signal based on the power state signal. The power stage includes a plurality of phase circuits coupled to the output node and is configured to enable a phase circuit of the plurality of phase circuits responsive to the control signal.

Abstract: The present invention provides an anisotropic, thermal conductive, electromagnetic interference (EMI) shielding composite including a plurality of aligned polymer nanofibers to form a polymer mat or scaffold having a first and second planes of orientation of the polymer nanofibers. The first plane of orientation of the polymer nanofibers has a thermal conductivity substantially the same as or similar to that of the second plane, and the thermal conductivity of the first or second plane of orientation of the polymer nanofibers is at least 2-fold of that of a third plane of orientation of the polymer nanofibers which is about 90 degrees out of the first and second planes of orientation of the polymer nanofibers, respectively, while the electrical resistance of each of the first and second planes is at least 3 orders lower than that of the third plane. A method for preparing the present composite is also provided.

Abstract: A semiconductor device includes an analog voltage regulator and an integrated circuit module. The analog voltage regulator generates a regulated output voltage. The integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (DVOC). The first sensor generates a digital reference voltage based on an analog reference voltage. The second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. The DVOC generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. The regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.