Patents by Inventor Mei See Chin

Mei See Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9978735
    Abstract: Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. Micro bumps of the mother die and the daughter die interface together to form a direct down connection between the mother die and the daughter die.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 22, 2018
    Assignee: Altera Corporation
    Inventors: Loke Yip Foo, Choong Kooi Chee, Mei See Chin, Wai Ling Lee, Wei Lun Oo
  • Publication number: 20180090474
    Abstract: Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. Micro bumps of the mother die and the daughter die interface together to form a direct down connection between the mother die and the daughter die.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: Loke Yip Foo, Choong Kooi Chee, Mei See Chin, Wai Ling Lee, Wei Lun Oo
  • Patent number: 9842181
    Abstract: The present disclosure relates to an innovative method of assigning signals to general-purpose input/output pads of an integrated circuit chip. An inductance matrix for the input/output pads is obtained. A candidate assignment is made of a differential signal to a pair of the input/output pads, and a differential mutual inductance is determined for each open pad location in relation to the pair of input/output pads. Single-ended signals are assigned to open pad locations having the lowest differential mutual inductances. The jitter contribution due to each assigned single-ended signal is computed, and a total jitter is updated. In a first embodiment, said assigning, computing and updating steps are repeated until the total jitter exceeds a total jitter budget. In a second embodiment, said assigning, computing and updating steps are repeated until a number of assigned single-ended signals is equal to a target number. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: December 12, 2017
    Assignee: Altera Corporation
    Inventors: Kyung Suk Oh, Yee Huan Yew, Chee Cheong Tan, Mei See Chin, Wai Ling Lee, Loke Yip Foo, Chooi Ian Loh, Hui Lee Teng