Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

Abstract: A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3? variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Abstract: A continuous liquid delivery system which includes at least one primary filter and at least one secondary filter for alternatively receiving a liquid such as a CMP polishing slurry. A primary backwash circuit is provided in fluid communication with each primary filter for backwashing of the primary filter. At least one secondary backwash circuit is provided in fluid communication with each secondary filter for backwashing of the secondary filter. As the liquid is distributed through the primary filter or filters, the secondary filter or filters can be backwashed, and vice-versa to facilitate a continuous flow of the liquid from a source to a destination.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Abstract: A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.

Abstract: An organic layer, such as a porous low-K dielectric in an IC, contains pores open at its surface. To close the pores, the organic layer is contacted by a supercritical fluid that is a solvent for the layer. After a small amount of the surface and the wall of the open pores is solvated, a phase transition of the solvated organic material is effected at the surface to cover it with a dense, smooth, non-porous film that seals the open pores.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Abstract: A new and improved method for exposing alignment marks on a substrate by locally cutting through a metal or non-metal layer or layers sequentially deposited on the substrate above the alignment marks, using focused ion beam (FIB) technology. In a preferred embodiment, a method for exposing alignment marks on a substrate can be carried out by first providing a substrate that has multiple alignment marks provided thereon and at least one overlying opaque layer, typically but not necessarily metal, deposited on the substrate above the alignment marks. A focused ion beam is then directed against the overlying opaque layer or layers to cut through the layer or layers and expose the alignment marks on the substrate. A noble gas, preferably argon, is typically used as the ion source for the focused ion beam.

Abstract: A method of integrating a post-etching cleaning process with deposition for a semiconductor device. A substrate having a damascene structure formed by etching a dielectric layer formed thereon using an overlying photoresist mask as an etching mask is provided. A cleaning process is performed by a supercritical fluid to remove the photoresist mask and post-etching by-products. An interconnect layer is formed in-situ in the damascene structure using the supercritical fluid as a reaction medium, wherein the cleaning process and the subsequent interconnect layer formation are performed in one process chamber or in different process chambers of a processing tool.

Abstract: A semiconductor device manufacturing system including a processing subsystem and a compensation thermal subsystem. The processing subsystem includes a process chamber and a thermal control subsystem having a processing subsystem heating element and configured to generate a process chamber temperature profile. The compensation thermal subsystem includes a temperature sensor configured to detect the process chamber temperature profile, a compensation thermal control unit (CTCU) configured to determine variation between the process chamber temperature profile and a desired temperature profile, and a compensation heating element configured to alter the process chamber temperature profile in response to the variation detected by the CTCU.

Abstract: A method of forming an oxide layer. A fluid, such as water, is heated and pressurized to supercritical or near-supercritical conditions and mixed with at least one oxidizing agent. The supercritical state mixture of the fluid and at least one oxidizing agent is then applied on the workpiece, forming an oxide layer on the workpiece. The at least one oxidizing agent may comprise nitrogen, and the oxide layer formed on the workpiece may comprise a nitrogen doped oxide.

Abstract: A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3? variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

Abstract: The present disclosure provides for a method and system for fabricating an insulating layer on a substrate. The method and system provide a fluid to a substrate, wherein the fluid is provided in an aerosol form. The method and system also provides for generating a supercritical process environment proximate to the substrate. The method and system further provides a proximate supercritical process environment having a supercritical process temperature and a supercritical process pressure for altering the fluid, and placing the substrate in contact with the altered fluid, wherein the insulating layer is formed on the substrate by a reaction between the substrate and the fluid.

Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “l”. The re-flowed first opening lower width “l” being less than the pre-re-flowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “l”. Removing the patterned, re-flowed masking layer.