Patents by Inventor Meikei Leong
Meikei Leong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7618857Abstract: A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.Type: GrantFiled: January 17, 2007Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: Meikei Leong, Qiqing C. Ouyang, Chun-Yung Sung
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Patent number: 7439109Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.Type: GrantFiled: November 9, 2005Date of Patent: October 21, 2008Assignee: International Business Machines CorporationInventors: Brent A. Anderson, MeiKei leong, Edward J. Nowak
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Publication number: 20080171413Abstract: A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Applicant: International Business Machines CorporationInventors: Meikei Leong, Qiqing C. Ouyang, Chun-Yung Sung
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Publication number: 20070218621Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: ApplicationFiled: April 10, 2007Publication date: September 20, 2007Applicant: International Business Machines CorporationInventors: Huiling Shang, Meikei Leong, Jack Chu, Kathryn Guarini
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Patent number: 7250658Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: GrantFiled: May 4, 2005Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Diane C. Boyd, Meikei Leong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang
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Patent number: 7161169Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: November 3, 2004Date of Patent: January 9, 2007Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Leong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Publication number: 20070001223Abstract: An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A plurality of impurities are segregated on the silicide/channel interface, and these segregated impurities determine the resistance of the Schottky contact. Such impurity segregation is achieved by a so called silicidation induced impurity segregation process. Silicon substitutional impurities are appropriate for accomplishing such a segregation.Type: ApplicationFiled: July 1, 2005Publication date: January 4, 2007Inventors: Diane Boyd, Meikei Leong, Jakub Kedzierski, Ghavam Shahidi
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Patent number: 7148559Abstract: An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction. The <110> direction is perpendicular to the <100> direction. A method of fabricating such as integrated semiconductor structure is also provided.Type: GrantFiled: June 20, 2003Date of Patent: December 12, 2006Assignee: International Business Machines CorporationInventors: Victor W. C. Chan, Meikei Leong, Min Yang
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Publication number: 20060076623Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.Type: ApplicationFiled: November 9, 2005Publication date: April 13, 2006Inventors: Brent Anderson, MeiKei Leong, Edward Nowak
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Publication number: 20060057787Abstract: A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.Type: ApplicationFiled: November 25, 2002Publication date: March 16, 2006Inventors: Bruce Doris, Dureseti Chidambarrao, Meikei Leong, Jack Mandelman
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Patent number: 6998684Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.Type: GrantFiled: March 31, 2004Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: Brent A. Anderson, MeiKei Leong, Edward J. Nowak
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Publication number: 20050224875Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.Type: ApplicationFiled: March 31, 2004Publication date: October 13, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent Anderson, MeiKei Leong, Edward Nowak
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Publication number: 20050106788Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: ApplicationFiled: December 2, 2004Publication date: May 19, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Katayun Barmak, Diane Boyd, Cyril Cabral, Meikei Leong, Thomas Kanarsky, Jakub Kedzierski
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Patent number: 6846734Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: GrantFiled: November 20, 2002Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Ricky Amos, Katayun Barmak, Diane C. Boyd, Cyril Cabral, Jr., Meikei Leong, Thomas S. Kanarsky, Jakub Tadeusz Kedzierski
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Publication number: 20050001290Abstract: An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction. The <110> direction is perpendicular to the <100> direction. A method of fabricating such as integrated semiconductor structure is also provided.Type: ApplicationFiled: June 20, 2003Publication date: January 6, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Meikei Leong, Min Yang
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Publication number: 20040094804Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Katayun Barmak, Diane C. Boyd, Cyril Cabral, Meikei Leong, Thomas S. Kanarsky, Jakub Tadeusz Kedzierski