Abstract: A method of managing the erasure of units of a flash memory. An indication is provided that an erasure of one or more units is pending, either before the units are erased or, in case of power loss, during the erasure. Subsequent to a completed erasure, an indication provided before an erasure is either erased or offset by an indication of a completed erasure. Upon powering up, or, in some embodiments, also prior to writing, the indications are inspected and units not completely erased are erased again. The present invention may be implemented in hardware, in firmware, in software, or in any combination of the three. In embodiments not totally reliant on software, appropriate non-volatile registers are provided, for storing the indications as erase pending flags and erase completed flags, and also for storing corresponding unit numbers.

Abstract: A datum is stored in a memory by placing a memory cell in a first state that is indicative of the datum, and later placing the same or a different cell in a second state that is indicative of the same datum. If a different cell is placed in the second state, both cells are programmed to store the same number of bits, and then preferably the first cell is erased. Preferably, the first cell is placed in the first state by the application thereto of a first train of voltage pulses until the cell's threshold voltage exceeds a first reference voltage, and the first or second cell is placed in the second state by the application thereto of a second train of voltage pulses until the cell's threshold voltage exceeds a second reference voltage.

Abstract: A compact high-speed data encoder/decoder for single-bit forward error-correction, and methods for same. This is especially useful in situations where hardware and software complexity is restricted, such as in a monolithic flash memory controller during initial startup and software loading, where robust hardware and software error correction is not feasible, and where rapid decoding is important. The present invention arranges the data to be protected into a rectangular array and determines the location of a single bit error in terms of row and column positions. So doing greatly reduces the size of lookup tables for converting error syndromes to error locations, and allows fast error correction by a simple circuit with minimal hardware allocation. Use of square arrays reduces the hardware requirements even further.

Abstract: A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the volatile memory and are executed by the CPU in the volatile memory. Preferably, the test results are stored in the nonvolatile memory.

Abstract: A memory device includes two dies. A first memory is fabricated on one die. A controller of the first memory is fabricated on the other die. Also fabricated on the other die is another component, such as a second memory, that communicates with a host system using a plurality of signals different from the signals used by the first memory. The device includes a single interface for communicating with the host system using only the respective signals of the second component. In a most preferred embodiment, the first memory is a NAND flash memory and the second memory is a SDRAM.

Abstract: An appliance that includes a host device and a memory unit with a primary memory, and a method of operating the appliance. According to one aspect of the appliance, the primary memory is nonvolatile and the memory unit also includes a volatile memory a power sensor and a controller. When the power sensor detects interruption of power to the memory unit, the controller copies data selectively from the volatile memory to the primary memory. Power for this copying is provided by a secondary power source such as a battery or a capacitor. According to another aspect of the appliance, the appliance includes primary and secondary power sources, and the memory unit also includes a charge pump whose functions include both boosting power from the primary source for the primary memory and charging the secondary source.

Abstract: A device, a method and a system for reading/writing data, preferably of a particular type, from a first dedicated port of a NVM storage, while other data is reading/written to at least a second general port of the NVM storage. Preferably, while data is being continually read/written through the dedicated port of the NVM storage, the logic processor which controls the NVM storage optionally “sleeps”, or reverts to a lower power consumption mode. The NVM storage of the present invention may optionally feature a plurality of ports, as long as at least one dedicated port for reading/writing data, preferably of a particular type, and at least one general port for reading/writing data, is provided. According to preferred embodiments of the present invention, the at least one dedicated ports is a port for reading/writing streamed data, such as streaming audio and/or video data for example.

Abstract: A processor that executes boot code in its cache memory, and a computer that includes the processor. The processor includes a download boot machine for retrieving the boot code from a sequential access memory device, such as a flash memory or a mass storage device, or from a random access memory such as a serial EEPROM.

Abstract: A device, a method and a system for reading/writing data, preferably of a particular type, from a first dedicated port of a NVM storage, while other data is reading/written to at least a second general port of the NVM storage. Preferably, while data is being continually read/written through the dedicated port of the NVM storage, the logic processor which controls the NVM storage optionally “sleeps”, or reverts to a lower power consumption mode. The NVM storage of the present invention may optionally feature a plurality of ports, as long as at least one dedicated port for reading/writing data, preferably of a particular type, and at least one general port for reading/writing data, is provided. According to preferred embodiments of the present invention, the at least one dedicated ports is a port for reading/writing streamed data, such as streaming audio and/or video data for example.

Abstract: A method of managing the erasure of units of a flash memory. An indication is provided that an erasure of one or more units is pending, either before the units are erased or, in case of power loss, during the erasure. Subsequent to a completed erasure, an indication provided before an erasure is either erased or offset by an indication of a completed erasure. Upon powering up, or, in some embodiments, also prior to writing, the indications are inspected and units not completely erased are erased again. The present invention may be implemented in hardware, in firmware, in software, or in any combination of the three. In embodiments not totally reliant on software, appropriate non-volatile registers are provided, for storing the indications as erase pending flags and erase completed flags, and also for storing corresponding unit numbers.