Patents by Inventor Meir Janai
Meir Janai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7590001Abstract: In certain exemplary embodiments, a memory device with optimized write sectors has a plurality P of memory write sectors and N memory spare sectors Cumulatively, the memory write sectors correspond to the specified storage capacity of the memory. The number N of spares is approximately equal to the number of write sectors expected to be decommissioned within an operational lifetime of the memory, which can be determined by empirical measurement. A method, by way of non-limiting example, of making memory includes specifying a plurality P of write sectors which define a specified storage capacity of a memory device, determining a number N of spare sectors, and making a memory device with about P write sectors and about N spare sectors. The number N can be determined, by way of example, by summing the infant mortality with the random failure of write sectors.Type: GrantFiled: December 18, 2007Date of Patent: September 15, 2009Assignee: Saifun Semiconductors Ltd.Inventor: Meir Janai
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Publication number: 20090154242Abstract: In certain exemplary embodiments, a memory device with optimized write sectors has a plurality P of memory write sectors and N memory spare sectors Cumulatively, the memory write sectors correspond to the specified storage capacity of the memory. The number N of spares is approximately equal to the number of write sectors expected to be decommissioned within an operational lifetime of the memory, which can be determined by empirical measurement. A method, by way of non-limiting example, of making memory includes specifying a plurality P of write sectors which define a specified storage capacity of a memory device, determining a number N of spare sectors, and making a memory device with about P write sectors and about N spare sectors. The number N can be determined, by way of example, by summing the infant mortality with the random failure of write sectors.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Inventor: Meir Janai
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Patent number: 6294927Abstract: This invention discloses a cell forming part of a customizable logic array device, the cell including at least first and second multiplexers, each having a select input and an output, at least two inverters, each having an input and an output, and electrical connections, selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the input of one of the at least two inverters. A customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers is also disclosed.Type: GrantFiled: June 16, 2000Date of Patent: September 25, 2001Assignee: Chip Express (Israel) LTDInventors: Uzi Yoeli, Meir Janai
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Patent number: 6255718Abstract: An integrated circuit coated with a layer of plasma deposited polymer which is ablatable by visible light laser radiation. The plasma layer is deposited on the circuit in a plasma chamber and the layer is ablated at selected locations.Type: GrantFiled: January 30, 1998Date of Patent: July 3, 2001Assignee: Chip Express CorporationInventors: Meir Janai, Yoram Cassuto, Michael Stephen Silverstein, Sharon Zehavi
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Patent number: 5861641Abstract: A customizable logic array device including an array of identical multiple input, function selectable logic cells comprising a first conductive layer, application configurable interconnection apparatus selectably interconnecting the multiple input, function selectable logic cells, the application configurable interconnection apparatus comprising at least two conductive layers.Type: GrantFiled: August 15, 1994Date of Patent: January 19, 1999Assignee: Quick Technologies Ltd.Inventors: Uzi Yoeli, Eran Rotem, Meir Janai, Zvi Orbach
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Patent number: 5818728Abstract: This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.Type: GrantFiled: March 15, 1996Date of Patent: October 6, 1998Assignee: Chip Express (Israel) Ltd.Inventors: Uzi Yoeli, Meir Janai, Zvi Orbach
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Patent number: 5751165Abstract: A very high speed customizable logic array device comprising:a substrate having at least one gate layer and at least first, second and third metal layers formed thereon, the gate layer including a multiplicity of identical unit logic cells,the customizable logic array device including at least three of the following functionalities:NAND, NOR, inverter, AND and ORand further being characterized in that the ratio between the rise time and the fall time of the logic cells embodying each of the at least three functionalities is constant.Type: GrantFiled: August 18, 1995Date of Patent: May 12, 1998Assignee: Chip Express (Israel) Ltd.Inventors: Uzi Yoeli, Eran Rotem, Meir Janai, Zvi Orbach
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Patent number: 5565758Abstract: This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.Type: GrantFiled: April 27, 1995Date of Patent: October 15, 1996Assignee: Chip Express (Israel) Ltd.Inventors: Uzi Yoeli, Meir Janai, Zvi Orbach
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Patent number: 5049969Abstract: A selectably customizable semconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer disposed in a second plane generally parallel to and electrically insulated from the first plane and including second elongate strips extending parallel to a second axis, the second axis being generally perpendicular to the first axis, whereby a multiplicity of elongate strip overlap locations are defined at which the elongate strips of the first and second metal layers overlap in electrical insulating relationship, the first metal layer including a plurality of fusible conductive bridges joining adjacent pairs of the first elongate strips, the fusible conductive bridges including first and second fusible links, the first metal layer also including a plurality of branch strips, each branch strip connecting one of the fusible conductive bridges at a location intermediate the first and second fusible links to a branch oType: GrantFiled: April 28, 1989Date of Patent: September 17, 1991Inventors: Zvi Orbach, Meir Janai, Uzi Yoeli, Gideon Amir
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Patent number: 3999990Abstract: An imaging method involves a substrate having a coating which undergoes a photochemical conversion upon being irradiated to yield only products whose vapor pressure under the operative temperature is higher than that of the coating. In this way as a result of the selective vaporization of the coating the desired image is obtained. The new method has wide applications such as photography, production of microfilms, electrophotographic document duplication, production of master prints for offset printing, etc.Type: GrantFiled: August 23, 1974Date of Patent: December 28, 1976Assignee: Technion Research and Development Foundation, Ltd.Inventors: Meir Janai, Peter S. Rudman