Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.