Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

Abstract: A pixel circuit, a driving method therefor, and a display apparatus. The pixel circuit includes a drive sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a light emitting element. The drive sub-circuit is configured to generate a drive current between a first electrode and a second electrode of the drive sub-circuit in response to a control signal of a first node; the first reset sub-circuit is configured to write a first reset signal to an anode terminal of the light emitting element in response to a signal of a first light emitting control signal line or a second reset control signal line; the second reset sub-circuit is configured to write a second reset signal to the first electrode or second electrode of the drive sub-circuit in response to a signal of a first reset control signal line; the second reset signal is greater than the first reset signal.

Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, a dielectric structure, and a spacer. The control gate and the select gate are over a channel region of the semiconductor substrate and separated from each other. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part. The select gate is between the spacer and the control gate, and the select gate is separated from the spacer by the second part of the dielectric structure.

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

Abstract: A user equipment includes reception circuitry configured to receive, from a base station, a PDCCH with a first DCI format, wherein the first DCI format schedules a PUSCH transmission; and control circuitry configured to perform the PUSCH transmission, in a case intra-slot frequency hopping is not enabled for the PUSCH transmission and a PUSCH repetition Type B is not applied to the PUSCH transmission, such that a first channel over which a first symbol on an antenna port used for an uplink transmission is conveyed can be inferred by the base station from a second channel over which a second symbol on the same antenna port is conveyed if the first symbol and the second symbol correspond to the same slot, and perform the PUSCH transmission in a case the PUSCH repetition Type B is applied to the PUSCH transmission, such that the first channel over which the first symbol on an antenna port used for an uplink transmission is conveyed can be inferred by the base station from the second channel over which the second

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

Abstract: A UE includes reception circuitry configured to receive PRACH configuration information comprising a first RSRP threshold and a first list of preamble index ranges, and control circuitry configured to, if one of one or more SSBs with SS-RSRP above the first RSRP threshold is available, select an SSB with SS-RSRP above the first RSRP threshold; else select any SSB, wherein in a first case that the PRACH configuration information further provides a second list of preamble index ranges, the control circuitry is further configured to select a preamble from the preamble index range associated with the selected SSB among the preamble index ranges in second list, in a second case that the PRACH configuration information does not provide the second list, the control circuitry is further configured to select a preamble from the preamble index range associated with the selected SSB among the preamble index ranges in the first list.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region which includes sub-pixels arranged in array, each sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extends in a first direction and include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row. A layer where the plurality of first reset signal lines are located is different from layers where the plurality of second reset signal lines are located.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: A method for preparing a semiconductor device includes: providing a semiconductor substrate, in which a trench is formed on the semiconductor substrate, a filling layer is formed in the trench, and a void is formed in the filling layer; removing a portion of the filling layer to expose the void; forming a plug, in which the plug is configured to plug the void and extends into the void by at least a preset distance; and removing a portion of the filling layer and remaining the plug with at least a preset height until the filling layer reaches a preset thickness to form a contact hole.

Abstract: The present invention discloses a display including a display panel and a light redirecting film disposed on the viewing side of the display panel. The light redirecting film comprises a light redistribution layer, and a light guide layer disposed on the light redistribution layer. The light redistribution layer includes a plurality of strip-shaped micro prisms extending along a first direction and arranged at intervals and a plurality of diffraction gratings arranged at the bottom of the intervals between the adjacent strip-shaped micro prisms, wherein each of the strip-shaped micro prisms has at least one inclined light-guide surface, and the bottom of each interval has at least one set of diffraction gratings, and the light guide layer is in contact with the strip-shaped micro prisms and the diffraction gratings.

Abstract: A method by a user equipment (UE) is described. The method includes receiving, from a base station, a first radio resource control (RRC) parameter including one or more entries, wherein each entry at least provides a value for ‘number of DMRS CDM groups without data’ and one value for one DMRS port index among one or more DMRS port indexes; and determining a bitwidth of an antenna port field in a DCI format at least based on a total count of the one or more entries included in the first RRC parameter; and receiving the DCI format with the antenna port field, wherein a value of the antenna port field indicates one of the one or more entries; and receiving a PDSCH scheduled by the DCI format based on the value of the ‘number of DMRS CDM groups without data’ and the DMRS port index associated to an entry corresponding to a value indicated in the antenna port field.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. In the display substrate, each signal line includes a first conductive portion; for at least one signal line, the display substrate includes a multi-layer insulating pattern on a side of the first conductive portion of each signal line away from the base substrate, and at least one insulating pattern covers a surface of a side of the first conductive portion away from the base substrate; a first insulating pattern in the multi-layer insulating pattern includes a hollow, and an orthographic projection of the hollow on the base substrate is at least partially in a region surrounded by an orthographic projection of the first conductive portion on the base substrate; and a material of the first insulating pattern includes an organic insulating material.

Abstract: An electronic device includes a display unit, a voltage generation unit, a grayscale adjustment unit, and an overdriving unit. The display unit has a relationship curve between the transmittance and the driving voltage. The relationship curve has a predetermined voltage value corresponding to the maximum transmittance. The voltage generation unit generates a first voltage according to a first grayscale, and generates a second voltage according to a second grayscale. The grayscale adjustment unit receives a first display grayscale value, and outputs the second grayscale value when the first display grayscale value is equal to the first grayscale. The overdriving unit overdrives the second voltage corresponding to the second grayscale to obtain a first target driving voltage, and it provides the first target driving voltage to the display unit.

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.