Abstract: The invention proposes a kind of bending bolt type anti-loosening nut, which relates to the technical field of mechanical fastening. It comprises an upper nut and a lower nut, the upper nut and the lower nut are stacked on the outside of the bolt and used to tightly connect the bolt to the connecting piece, the lower nut is arranged close to the connecting piece, the upper nut is arranged on the outer end surface of the lower nut; the adjacent end between the upper nut and lower nut is provided with an inclined surface, the inclined surface is inclined towards the interior of the upper nut, so that an inclined plane angle with deformation space between the upper nut and lower nut is formed; the invention achieves the effect of preventing nut loosening, is low in price, easy to manufacture, and suitable for small or miniature anti-loosening nuts.

Abstract: A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.

Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

Abstract: A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.

Abstract: A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.

Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

Abstract: This application discloses an audio data processing method and apparatus, and relates to the field of multimedia technologies. The method includes: obtaining m (m is an integer greater than or equal to 2) audio clips; determining m?1 pieces of transition audio information based on the m audio clips; and generating target medley audio based on the m audio clips and the m 1 pieces of transition audio information. The m?1 pieces of transition audio information are used to splice the m audio clips. First transition audio information in the m?1 pieces of transition audio information is used to splice a first audio clip and a second audio clip that are sorted consecutively in the m audio clips. Sorting of the m audio clips is a medley composition order of the m audio clips.

Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.

Abstract: Disclosed in the present invention is an anti-Nipah virus monoclonal antibody having neutralization activity. The antibody consists of a monkey-derived variable region and a human constant region, and both light and heavy chains of the monkey-derived variable region have unique CDR regions. The antibody provided by the present invention has an excellent antigen binding capability, and has good binding activity with Bangladesh Nipah virus and Malaysia Nipah virus glycoprotein G. The antibody can effectively neutralize the Nipahpseudovirus. Moreover, the neutralization activity of the antibody is enhanced as the concentration of the antibody increases, and nearly 100% neutralization of the Nipahpseudovirus can be achieved at a concentration of 1 ?g/mL. Also disclosed in the present invention is an application of the monoclonal antibody against the Nipah virus glycoprotein G in preparation of a Nipah virus treatment drug.

Abstract: A computing circuit is provided. The computing circuit is disposed in a memory device and electrically coupled to a memory cell of the memory device. The computing circuit includes a weight decoder, a multiplier, an adder tree, and an accumulator. The weight decoder is configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight. The multiplier is configured to generate a partial-product by multiplying an input signal with the decoded weight. The adder tree is configured to generate a partial-sum by performing an addition operation based on the partial-product. The accumulator is configured to generate an accumulated sum by performing an accumulation operation based on the partial-sum and output an output signal based on the accumulated sum. The accumulated sum is left shifted based on a shift signal.

Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

Abstract: A memory device includes a memory array, a multiply-accumulate (MAC) circuit and an encoder-decoder circuit. The MAC circuit performs a MAC operation on an encoded weight data stored in the memory array and an input data to generate a partial MAC result. An encoder of the encoder-decoder circuit is configured to encode m weight bits among n weight bits of weight data according to an encryption key to generate the encoded weight data, wherein m and n are positive integers, and m is less than n. A decoder of the encoder-decoder circuit is configured to detect an error in the partial MAC result according to the encryption key to generate a decoded partial MAC result.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: A system for testing an assist function of electric vehicle wireless power transfer includes: a pit, a vehicle-assembly support platform, and an electromagnetic field strength measurement instrument. A ground-assembly support platform is arranged inside the pit, the vehicle-assembly support platform is arranged on an upper side of the ground-assembly support platform, and a to-be-tested member is arranged on an upper side of the ground-assembly support platform. A ground-assembly device coil is arranged on an upper surface of the ground-assembly support platform, a vehicle-assembly device coil is arranged inside the vehicle-assembly support platform, the ground-assembly device coil charges an entire vehicle, and the ground-assembly device coil further cooperates with the vehicle-assembly device coil to charge a vehicle component. A mechanical arm is arranged on ground of a test site, an interference member is arranged on a front end of the mechanical arm.

Abstract: An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time-to-digital convertor converts a time associated with the output voltage to a digital value.

Abstract: A circuit includes a reference voltage node, first and second data lines, a sense amplifier, first and second switching devices coupled between the first and second data lines and first and second input terminals of the sense amplifier, third and fourth switching devices coupled between the first and second data lined and first and second nodes, fifth and sixth switching devices coupled between the first and second nodes and the reference voltage node, and first and second capacitive devices coupled between the first and second nodes and second and first input terminals. Each of the first through fourth switching devices is switched on and each of the fifth and sixth switching devices is switched off in a first operational mode, and each of the first through fourth switching devices is switched off and each of the fifth and sixth switching devices is switched on in a second operational mode.

Abstract: A meme creation method and apparatus are provided, and relate to the terminal field, to enrich forms and content of memes, and improve user experience. The method includes: displaying a first interface, where the first interface includes a speech input button; receiving, in response to an operation of triggering the speech input button by a user, a speech input by the user; recognizing the speech in a preset manner, where recognition in the preset manner includes at least content recognition, and if the speech includes a target keyword, recommending a first image meme set to the user; obtaining, in response to an operation of selecting one image meme from the first image meme set by the user, a target meme based on the image meme selected by the user and the speech or semantics corresponding to the speech; and sending the target meme.

Abstract: A system for testing an assist function of electric vehicle wireless power transfer includes: a pit, a vehicle-assembly support platform, and an electromagnetic field strength measurement instrument. A ground-assembly support platform is arranged inside the pit, the vehicle-assembly support platform is arranged on an upper side of the ground-assembly support platform, and a to-be-tested member is arranged on an upper side of the ground-assembly support platform. A ground-assembly device coil is arranged on an upper surface of the ground-assembly support platform, a vehicle-assembly device coil is arranged inside the vehicle-assembly support platform, the ground-assembly device coil charges an entire vehicle, and the ground-assembly device coil further cooperates with the vehicle-assembly device coil to charge a vehicle component. A mechanical arm is arranged on ground of a test site, an interference member is arranged on a front end of the mechanical arm.

Abstract: This application relates to the artificial intelligence (AI) field, and specifically, to a voice quality enhancement method and a related device. The method includes: after a PNR mode is enabled, obtaining a noisy voice signal and target voice-related data, where the noisy-carrying voice signal includes a voice signal of a target user and an interfering noise signal, and the target voice-related data indicates a voice feature of the target user; and performing noise reduction on the noisy voice signal based on the target voice-related data by using a trained voice noise reduction model to obtain a noise-reduced voice signal of the target user, where the voice noise reduction model is implemented based on a neural network. In embodiments of this application, voice of a target person can be enhanced, and interference can be suppressed.