Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: In a method for forming an integrated semiconductor device, a first transistor over is formed on a substrate; an inter-layer dielectric (ILD) layer is deposited over the first transistor; a gate conductive layer is deposited over the ILD layer; a gate dielectric layer is deposited over the gate conductive layer; the gate dielectric layer and the gate conductive layer are etched to form a gate stack; and a 2D material layer that has a first portion extending along a top surface and sidewalls of the gate stack and a second portion extending along a top surface of the ILD layer.

Abstract: Present disclosure provides gate-all-around structure including a semiconductor fin having a top surface, a first nanowire over the top surface, a first space between the top surface and the first nanowire, an Nth nanowire and an (N+1)th nanowire over the first nanowire, and a second space between the Nth nanowire and the (N+1)th nanowire. The first space is greater than the second space. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.

Abstract: A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.

Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer, The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si1?x?yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, and 0.01?x?0.1, and 0.01?y?0.1.

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0<a, 0<b, 0.01?(a+b)?0.1, 0.01?y?0.1, and M2 is P or As.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: An integrated semiconductor device includes a first semiconductor device, an ILD layer and a second semiconductor device. The first semiconductor device has a first transistor structure. The ILD layer is over the first semiconductor device and has a thickness in a range substantially from 10 nm to 100 nm. The second semiconductor device is over the ILD layer and has a 2D material layer as a channel layer of a second transistor structure thereof.

Abstract: A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a first fin and a second fin formed over the substrate. The semiconductor structure further includes a first anti-punch through region formed in the first fin and a second anti-punch through region formed in the second fin and first nanostructures formed over the first fin and second nanostructures formed over the second fin. The semiconductor structure further includes a barrier layer formed over the second anti-punch through region and a first gate formed around the first nanostructures. The semiconductor structure further includes a second gate formed around the second nanostructures. In addition, an interface between the barrier layer and the second anti-punch through region is higher than an interface between the first anti-punch through region and the first gate.

Abstract: A semiconductor device includes a fin structure extending along a first direction, a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, a gate stack extending across the channel layer along a second direction perpendicular to the first direction, and a spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction. The channel layer includes a two-dimensional material. The gate stack includes a ferroelectric layer.

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

Abstract: A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: Present disclosure provides a semiconductor structure including a first transistor and a second transistor. The first transistor includes a semiconductor substrate having a top surface and a first anti-punch through region doped with a first conductivity dopant at the top surface. The first transistor further includes a first channel over the top surface of the semiconductor substrate by a first distance. The second transistor includes a second anti-punch through region doped with a second conductivity dopant at the top surface of the semiconductor substrate. The second transistor further includes a second channel over the top surface of the semiconductor substrate by a second distance greater than the first distance. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Abstract: The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.