Patents by Inventor Meng-Hsuan Wu
Meng-Hsuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11962308Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.Type: GrantFiled: June 22, 2023Date of Patent: April 16, 2024Assignee: M31 TECHNOLOGY CORPORATIONInventors: Hui Huan Wang, Meng Hsuan Wu
-
Publication number: 20240032871Abstract: A digital filtering method is applicable to a photoplethysmography (PPG) device. The PPG device samples a mixed-light signal M time(s) to obtain M mixed-light digital value(s), and samples an ambient-light signal N time(s) to obtain N ambient-light digital value(s), wherein each mixed-light digital value includes a controllable-light component and an ambient-light component. The method includes: preparing a digital filter whose filter order is (M+N?1); using the digital filter to multiply the M mixed-light digital value(s) by M coefficient(s) respectively and thereby generate M value(s); using the digital filter to multiply N ambient-light digital value(s) by N coefficient(s) respectively and thereby generate N value(s); and using the digital filter to add up the M value(s) and the N value(s) and thereby generate an output value.Type: ApplicationFiled: June 28, 2023Publication date: February 1, 2024Inventor: MENG-HSUAN WU
-
Publication number: 20230336180Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.Type: ApplicationFiled: June 22, 2023Publication date: October 19, 2023Inventors: HUI HUAN WANG, MENG HSUAN WU
-
Publication number: 20230274072Abstract: A method includes identifying a cell in the layout diagram as a violated cell that fails to pass one or more design rules related to IR drops, and classifying a root cause of the violated cell with a root cause class. The method also includes determining a searching area for searching safe region candidates, and finding a selected cell for moving based upon the root cause class of the root cause. The method further includes finding a safe region in the searching area for moving the selected cell, and moving the selected cell to the safe region if the safe region is found within the searching area.Type: ApplicationFiled: March 10, 2022Publication date: August 31, 2023Inventors: Fa ZHOU, JinXin LIU, Chieh-Fu CHU, Yen-Feng SU, Chia-Chun LIAO, Meng-Hsuan WU, Dei-Pei LIU
-
Patent number: 11736109Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.Type: GrantFiled: June 23, 2021Date of Patent: August 22, 2023Assignee: M31 TECHNOLOGY CORPORATIONInventors: Hui Huan Wang, Meng Hsuan Wu
-
Publication number: 20230255492Abstract: A wound analyzing system is provided. An illumination device provides visible light and infrared light. An image sensor captures an infrared-light image, a red-light image and a visible-light image about a wound. A processor performs an image segmentation algorithm on the visible-light image to obtain a wound part and a background part, and classifies the wound part into one of multiple types. The processor calculates a blood-oxygen-concentration image according to the red-light image and the infrared-light image, aligns the visible-light image and the blood-oxygen-concentration image, and calculates a wound index and a wound healing stage according to the blood oxygen concentration values and the type corresponding to the wound part.Type: ApplicationFiled: August 31, 2022Publication date: August 17, 2023Inventors: Chih-Lung LIN, Meng-Hsuan WU
-
Publication number: 20230053711Abstract: A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.Type: ApplicationFiled: September 21, 2021Publication date: February 23, 2023Inventors: Qiuyuan WU, Shuang DAI, Chia-Chun LIAO, Meng-Hsuan WU
-
Patent number: 11418209Abstract: A signal conversion circuit includes a first pair of capacitors and a comparator. The first pair of capacitors includes a first capacitor and a second capacitor having a same capacitance value. Each of the first capacitor and the second capacitor is coupled to an input signal during a first sampling phase, while uncoupled from the input signal during a first conversion phase after the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal, and the comparator is configured to compare a signal level at the first input terminal and a signal level at the second input terminal to convert the input signal.Type: GrantFiled: April 6, 2021Date of Patent: August 16, 2022Assignee: M31 TECHNOLOGY CORPORATIONInventors: Hui Huan Wang, Meng Hsuan Wu
-
Publication number: 20210399735Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.Type: ApplicationFiled: June 23, 2021Publication date: December 23, 2021Inventors: HUI HUAN WANG, MENG HSUAN WU
-
Publication number: 20210313998Abstract: A signal conversion circuit includes a first pair of capacitors and a comparator. The first pair of capacitors includes a first capacitor and a second capacitor having a same capacitance value. Each of the first capacitor and the second capacitor is coupled to an input signal during a first sampling phase, while uncoupled from the input signal during a first conversion phase after the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal, and the comparator is configured to compare a signal level at the first input terminal and a signal level at the second input terminal to convert the input signal.Type: ApplicationFiled: April 6, 2021Publication date: October 7, 2021Inventors: HUI HUAN WANG, MENG HSUAN WU
-
Patent number: 8599059Abstract: A SAR ADC converting an analog signal into a digital signal having N bits counting from a most significant bit to a least significant bit includes a comparator comparing a positive component with a negative component of the analog signal, two CDACs and a logic circuit. For at least one i-th bit cycle of N bit cycle except a least significant bit cycle, one of a pair of capacitors relating to (i+1)-th bit respectively arranged in the two CDACs is switched according to a first comparing result of the comparator. After one of the pair of capacitors is switched, the comparator compares the positive component with the negative component of the analog signal again and generates a second comparing result. Then whether each one of capacitors relating to i-th bit in the two CDAC is to be switched is determined according to the first and the second comparing result.Type: GrantFiled: September 14, 2012Date of Patent: December 3, 2013Assignee: Mediatek Inc.Inventors: Yung-Hui Chung, Meng-Hsuan Wu
-
Patent number: 8508400Abstract: A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.Type: GrantFiled: May 23, 2012Date of Patent: August 13, 2013Assignee: Mediatek Inc.Inventors: Meng Hsuan Wu, Yung-Hui Chung
-
Patent number: 8466824Abstract: A current providing system, for providing an output current, which comprises: a frequency detecting circuit, for receiving at least one input signal, and for detecting a frequency of the input signal; a frequency-controlled current providing circuit, for providing the output current according to the input signal frequency when the input signal frequency is in a first predetermined range; and a predetermined current providing circuit, for providing the output current with a first predetermined current value, when the input signal frequency is not in the first predetermined range.Type: GrantFiled: June 2, 2011Date of Patent: June 18, 2013Assignee: Faraday Technology Corp.Inventors: Yen-Hsin Chu, Meng-Hsuan Wu
-
Publication number: 20120326900Abstract: A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.Type: ApplicationFiled: May 23, 2012Publication date: December 27, 2012Applicant: MEDIATEK INC.Inventors: Meng Hsuan WU, Yung-Hui CHUNG
-
Publication number: 20120306680Abstract: A current providing system, for providing an output current, which comprises: a frequency detecting circuit, for receiving at least one input signal, and for detecting a frequency of the input signal; a frequency-controlled current providing circuit, for providing the output current according to the input signal frequency when the input signal frequency is in a first predetermined range; and a predetermined current providing circuit, for providing the output current with a first predetermined current value, when the input signal frequency is not in the first predetermined range.Type: ApplicationFiled: June 2, 2011Publication date: December 6, 2012Inventors: Yen-Hsin Chu, Meng-Hsuan Wu