Patents by Inventor Meng-Jung Chuang

Meng-Jung Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230043018
    Abstract: A smart ring includes a battery, memory, processing circuitry, a plurality of sensors, a plurality of antennas, and a battery, each coupled to one another and all enclosed in a casing, wherein the processing circuitry is configured to conserve the battery by any of sending data to the cloud service when an application is open on the user device, sending data to the cloud service when a threshold is crossed, waking up processing or communicating when there is a change in motion detected by the accelerometer.
    Type: Application
    Filed: April 6, 2022
    Publication date: February 9, 2023
    Inventors: Crystal Wai, Shuhan Liu, Hsiangyin Cheng, Meng-Jung Chuang, Liem Hieu Dinh Vo, Richard Chang, Ming-Tsung Su, Hao-Hsiu Huang, Jeffrey ChiFai Liew, Zhicheng Qiu, Cuong Vu, Fahri Diner, Miroslav Samardzija, Shu Chun Shen
  • Publication number: 20220238502
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Application
    Filed: April 12, 2022
    Publication date: July 28, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yueh TSAI, Meng-Jen WANG, Yu-Fang TSAI, Meng-Jung CHUANG
  • Patent number: 11302682
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yueh Tsai, Meng-Jen Wang, Yu-Fang Tsai, Meng-Jung Chuang
  • Publication number: 20210125974
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yueh TSAI, Meng-Jen WANG, Yu-Fang TSAI, Meng-Jung CHUANG
  • Patent number: 7473629
    Abstract: A substrate structure having a solder mask and a process for making the same, including (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. The substrate structure can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: January 6, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Chang Tai, Chi-Chih Chu, Meng-Jung Chuang, Cheng-Yin Lee, Yao-Ting Huang, Kuang-Lin Lo
  • Patent number: 7417329
    Abstract: A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: August 26, 2008
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Jung Chuang, Cheng-Yin Lee, Wei-Chang Tai, Chi-Chih Chu
  • Publication number: 20070243704
    Abstract: The present invention relates to a substrate structure having a solder mask and a process for making the same. The process comprises: (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. Whereby, the substrate structure of the invention can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.
    Type: Application
    Filed: December 6, 2006
    Publication date: October 18, 2007
    Inventors: Wei-Chang Tai, Chi-Chih Chu, Meng-Jung Chuang, Cheng-Yin Lee, Yao-Ting Huang, Kuang-Lin Lo
  • Publication number: 20070132093
    Abstract: A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.
    Type: Application
    Filed: May 25, 2006
    Publication date: June 14, 2007
    Inventors: Meng-Jung Chuang, Cheng-Yin Lee, Wei-Chang Tai, Chi-Chih Chu
  • Patent number: D743730
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: November 24, 2015
    Assignee: PEGATRON CORPORATION
    Inventors: Ching-Chen Yang, Meng-Jung Chuang, Kai-Chi Yao