Patents by Inventor Meng-Kai Hsu
Meng-Kai Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10977420Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.Type: GrantFiled: December 23, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Meng-Kai Hsu, Wen-Hao Chen
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Patent number: 10943046Abstract: A semiconductor apparatus includes a first cell having a first interconnect structure and a second cell having a second interconnect structure. The semiconductor apparatus further includes a first plurality of conductive segments, wherein each conductive segment of the first plurality of conductive segments directly connects a first metal level of the first interconnect structure to a first metal level of the second interconnect structure. The semiconductor apparatus further includes a third cell having a third interconnect structure and a fourth cell having a fourth interconnect structure. The semiconductor apparatus further includes a second plurality of conductive segments, wherein each conductive segment of the second plurality of conductive segments directly connects a second metal level of the third interconnect structure to a second metal level of the fourth interconnect structure, and the second metal level is different from the first metal level.Type: GrantFiled: October 21, 2019Date of Patent: March 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Prasenjit Ray, Lee-Chung Lu, Meng-Kai Hsu, Wen-Hao Chen, Yuan-Te Hou
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Publication number: 20200380194Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.Type: ApplicationFiled: August 19, 2020Publication date: December 3, 2020Inventors: Meng-Kai HSU, Sheng-Hsiung CHEN, Wai-Kei MAK, Ting-Chi WANG, Yu-Hsiang CHENG, Ding-Wei HUANG
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Patent number: 10776551Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.Type: GrantFiled: June 14, 2019Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Meng-Kai Hsu, Sheng-Hsiung Chen, Wai-Kei Mak, Ting-Chi Wang, Yu-Hsiang Cheng, Ding-Wei Huang
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Patent number: 10713410Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.Type: GrantFiled: April 25, 2019Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chao-Hung Wang, Yen-Yi Wu, Shih-Chun Chen, Yao-Wen Chang, Meng-Kai Hsu
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Patent number: 10643017Abstract: A method is disclosed that includes: if there is a conflict graph including a sub-graph representing that each spacing between any two of three adjacent patterns of quadruple-patterning (QP) patterns in at least one of two abutting cells is smaller than a threshold spacing, performing operations including: identifying if one of edges that connect the three adjacent patterns of QP patterns to one another is constructed along, and/or in parallel with, a boundary between the two abutting cells; modifying multiple-patterning patterns of a layout of an integrated circuit (IC) to exclude patterns representing the sub-graph; and initiating generation of the IC from the modified multiple-patterning patterns, wherein at least one operation of identifying, modifying, or initiating is performed by at least one processor.Type: GrantFiled: April 25, 2018Date of Patent: May 5, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Kai Hsu, Yuan-Te Hou, Wen-Hao Chen
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Publication number: 20200125787Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Inventors: Meng-Kai Hsu, Wen-Hao Chen
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Publication number: 20200050733Abstract: A semiconductor apparatus includes a first cell having a first interconnect structure and a second cell having a second interconnect structure. The semiconductor apparatus further includes a first plurality of conductive segments, wherein each conductive segment of the first plurality of conductive segments directly connects a first metal level of the first interconnect structure to a first metal level of the second interconnect structure. The semiconductor apparatus further includes a third cell having a third interconnect structure and a fourth cell having a fourth interconnect structure. The semiconductor apparatus further includes a second plurality of conductive segments, wherein each conductive segment of the second plurality of conductive segments directly connects a second metal level of the third interconnect structure to a second metal level of the fourth interconnect structure, and the second metal level is different from the first metal level.Type: ApplicationFiled: October 21, 2019Publication date: February 13, 2020Inventors: Prasenjit RAY, Lee-Chung LU, Meng-Kai HSU, Wen-Hao CHEN, Yuan-Te HOU
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Publication number: 20200004912Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.Type: ApplicationFiled: June 14, 2019Publication date: January 2, 2020Inventors: Meng-Kai HSU, Sheng-Hsiung CHEN, Wai-Kei MAK, Ting-Chi WANG, Yu-Hsiang CHENG, Ding-Wei HUANG
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Patent number: 10515186Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.Type: GrantFiled: April 29, 2019Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Meng-Kai Hsu, Wen-Hao Chen
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Patent number: 10452805Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array, the latter including a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The crowning includes disposing vias in a VIA(N+1) layer so as to be substantially collinear (relative to a first direction), and not substantially collinear (relative to a substantially perpendicular second direction), with corresponding vias in the VIA(N) layer.Type: GrantFiled: November 30, 2018Date of Patent: October 22, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Prasenjit Ray, Lee-Chung Lu, Meng-Kai Hsu, Wen-Hao Chen, Yuan-Te Hou
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Publication number: 20190286784Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.Type: ApplicationFiled: March 12, 2019Publication date: September 19, 2019Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
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Publication number: 20190251224Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.Type: ApplicationFiled: April 25, 2019Publication date: August 15, 2019Inventors: Chao-Hung WANG, Yen-Yi WU, Shih-Chun CHEN, Yao-Wen CHANG, Meng-Kai HSU
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Publication number: 20190251228Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Meng-Kai Hsu, Wen-Hao Chen
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Patent number: 10275559Abstract: A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.Type: GrantFiled: November 18, 2016Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hung Wang, Yen-Yi Wu, Shih-Chun Chen, Yao-Wen Chang, Meng-Kai Hsu
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Patent number: 10275562Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.Type: GrantFiled: March 13, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Meng-Kai Hsu, Wen-Hao Chen
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Publication number: 20190108305Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array, the latter including a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The crowning includes disposing vias in a VIA(N+1) layer so as to be substantially collinear (relative to a first direction), and not substantially collinear (relative to a substantially perpendicular second direction), with corresponding vias in the VIA(N) layer.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: Prasenjit RAY, Lee-Chung LU, Meng-Kai HSU, Wen-Hao CHEN, Yuan-Te HOU
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Patent number: 10169520Abstract: A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array. Each standard second array includes a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The method further includes: adding, to the M(N+Q) layer, second segments which connect corresponding first segments of the M(N+Q) metallization layer in the corresponding second standard arrays.Type: GrantFiled: March 28, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Prasenjit Ray, Lee-Chung Lu, Meng-Kai Hsu, Wen-Hao Chen, Yuan-Te Hou
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Patent number: 10162929Abstract: The present disclosure is directed to systems and methods for using multiple libraries with different cell pre-coloring. In embodiments, the present disclosure determines a first set of cells to be placed using a single library methodology for pre-coloring and a second set of cells to be placed using a multiple library methodology for pre-coloring. In further embodiments, color-aware cell swapping can be performed based on the first set of cells and the second set of cells to align cells to swap the pre-coloring arrangements of cells to align with a track color of a closest legalization site candidate.Type: GrantFiled: May 3, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Kai Hsu, Yuan-Te Hou, Wen-Hao Chen
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Patent number: 10140407Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.Type: GrantFiled: November 26, 2014Date of Patent: November 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ming Ho, Adari Rama Bhadra Rao, Meng-Kai Hsu, Kuang-Hung Chang, Ke-Ying Su, Wen-Hao Chen, Hsien-Hsin Sean Lee