Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

Abstract: A memory device includes a plurality of resistive random access memory (RRAM) cells commonly connected between a bit line (BL) and a source line (SL). Each of the RRAM cells includes a resistor, a first transistor, and a second transistor coupled to each other in series, with the resistor connected to the BL and the second transistor connected to the SL. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage, the first threshold voltage being less than the second threshold voltage.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: The present disclosure includes a voltage provision circuit. In one aspect of the present disclosure, a voltage provision circuit is disclosed. The voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage. The voltage provision circuit includes a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage. The voltage provision circuit includes a first PMOS transistor sourced with a first supply voltage. The voltage provision circuit includes a second PMOS transistor sourced with the first supply voltage. The voltage provision circuit includes a voltage modulation circuit, coupled between the first to second PMOS transistors and the first to second NMOS transistors, that is configured to provide a first intermediate signal based on the first and second control signals.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

Abstract: An OTP memory cell is provided. The OTP memory cell includes: an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line having a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal; and a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line having a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal. A first terminal of the antifuse transistor is a vacancy terminal, and a second terminal of the antifuse transistor is connected to the selection transistor.

Abstract: A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.

Abstract: An IC structure includes a first active area including a first plurality of fin structures extending in a first direction, a second active area including a second plurality of fin structures extending in the first direction, an electrical fuse (eFuse) extending in the first direction between the first and second active areas and electrically connected to each of the first and second pluralities of fin structures, a first plurality of gate structures extending over the first active area perpendicular to the first direction, a second plurality of gate structures extending over the second active area in the second direction, a first signal line extending in the first direction adjacent to the first active area and electrically connected to the first plurality of gate structures, and a second signal line extending in the first direction adjacent to the second active area and electrically connected to the second plurality of gate structures.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.

Abstract: An information handling system includes a host processing system and a Liquid Crystal Display device. The host processing system includes a graphics processing unit (GPU) and the LCD device includes a memory device and a DisplayPort Configuration Data (DPCD) register. The host processing system 1) determines whether the first GPU supports a Dynamic Display Shifting (DDS) mode, 2) when the GPU does not support the DDS mode, provides a first indication to the LCD device that the GPU does not support the DDS mode, and 3) when the GPU supports the DDS mode, provides a second indication to the LCD device that the GPU supports the DDS mode. The LCD device retrieves a Panel Self Refresh (PSR) setting from the memory device and stores the PSR setting to the DPCD register in response to the first indication, and retrieves a DDS setting from the memory and stores the DDS setting to the DPCD register in response to the second indication.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.

Abstract: A memory device includes a plurality of one-time-programmable (OTP) memory cells formed as a memory array. Each of the plurality of OTP memory cells includes a transistor and a metal structure electrically coupled to each other in series, and the plurality of OTP memory cells are formed on a first side of a substrate. The memory device includes a heater structure, disposed on a second side of the substrate opposite to the first side, that includes a plurality of interconnect structures. The plurality of interconnect structures are configured to conduct a substantially high current so as to elevate a temperature of the resistor when any of the OTP memory cells is being programmed.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.