Patents by Inventor Meng-Tsung Lee
Meng-Tsung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933817Abstract: A probe card device and a transmission structure are provided. The transmission structure includes a supporting layer, a plurality of metal conductors spaced apart from each other and slantingly inserted into the supporting layer, and an insulating resilient layer formed on the supporting layer. Each of the metal conductors includes a positioning segment held in the supporting layer, a connecting segment and an embedded segment respectively extending from two ends of the positioning segment, and an exposed segment extending from the embedded segment. Each of the embedded segments is embedded and fixed in the insulating resilient layer, and each of the exposed segments protrudes from the insulating resilient layer. When any one of the exposed segments is pressed by an external force, the insulating resilient layer is configured to absorb the external force through the corresponding embedded segment so as to have a deformation providing a stroke distance.Type: GrantFiled: January 13, 2022Date of Patent: March 19, 2024Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.Inventors: Wen-Tsung Lee, Hsun-Tai Wei, Pang-Chi Huang, Meng-Chieh Cheng
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Patent number: 10199331Abstract: A method for fabricating an electronic package is provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.Type: GrantFiled: January 30, 2018Date of Patent: February 5, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Meng-Tsung Lee, Fu-Tang Huang
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Patent number: 10192838Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.Type: GrantFiled: January 20, 2017Date of Patent: January 29, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Lung Chuang, Po-Yi Wu, Meng-Tsung Lee, Yih-Jenn Jiang
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Patent number: 10049955Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.Type: GrantFiled: April 26, 2017Date of Patent: August 14, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Publication number: 20180158784Abstract: A method for fabricating an electronic package is provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.Type: ApplicationFiled: January 30, 2018Publication date: June 7, 2018Inventors: Meng-Tsung Lee, Fu-Tang Huang
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Patent number: 9899237Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.Type: GrantFiled: February 7, 2014Date of Patent: February 20, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Patent number: 9875981Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.Type: GrantFiled: October 19, 2016Date of Patent: January 23, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
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Patent number: 9812340Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.Type: GrantFiled: March 18, 2016Date of Patent: November 7, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
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Publication number: 20170229364Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.Type: ApplicationFiled: April 26, 2017Publication date: August 10, 2017Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Publication number: 20170133337Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.Type: ApplicationFiled: January 20, 2017Publication date: May 11, 2017Inventors: Chien-Lung Chuang, Po-Yi Wu, Meng-Tsung Lee, Yih-Jenn Jiang
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Publication number: 20170077047Abstract: An electronic device package and manufacturing method are provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.Type: ApplicationFiled: December 29, 2015Publication date: March 16, 2017Inventors: Meng-Tsung Lee, Fu-Tang Huang
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Publication number: 20170040277Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.Type: ApplicationFiled: October 19, 2016Publication date: February 9, 2017Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
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Patent number: 9502333Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.Type: GrantFiled: October 17, 2013Date of Patent: November 22, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
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Publication number: 20160196990Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.Type: ApplicationFiled: March 18, 2016Publication date: July 7, 2016Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
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Patent number: 9324585Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.Type: GrantFiled: October 18, 2012Date of Patent: April 26, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
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Patent number: 9041189Abstract: A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements.Type: GrantFiled: October 24, 2012Date of Patent: May 26, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Meng-Tsung Lee, Chiang-Cheng Chang, Shih-Kuang Chiu
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Publication number: 20150072517Abstract: A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.Type: ApplicationFiled: September 16, 2014Publication date: March 12, 2015Inventors: Yi-Hung Lin, Meng-Tsung Lee, Sui-An Kao, Yi-Hsin Chen, Feng-Lung Chien
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Patent number: 8866293Abstract: A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.Type: GrantFiled: June 23, 2011Date of Patent: October 21, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yi-Hung Lin, Meng-Tsung Lee, Sui-An Kao, Yi-Hsin Chen, Feng-Lung Chien
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Publication number: 20140252603Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.Type: ApplicationFiled: October 17, 2013Publication date: September 11, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
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Publication number: 20140154842Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.Type: ApplicationFiled: February 7, 2014Publication date: June 5, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu