Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

Abstract: A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: In some implementations, a memory device may receive a write command that includes data to be written to multiple memory pages of a translation unit (TU) of the memory device. The multiple memory pages of the TU may span multiple memory planes of the memory device. The memory device may identify the multiple memory pages of the TU, to which the data is to be written, based on one or more bad blocks of the memory device and a determination of whether one or more memory pages of the memory device are to be reserved. The memory device may write the data to the multiple memory pages of the TU.

Abstract: A gas permeable metal with a porosity gradient and a method of manufacturing the same are provided. A second lamination layer and a third lamination layer are respectively connected to two opposite sides of a first lamination layer. A pore diameter of the first lamination layer is larger than that of the second lamination layer. Thereby while being applied to molds, a mold cavity is mounted in the second lamination layer with smaller pore diameter so that products formed have fine and smooth surfaces. The arrangement of the first lamination layer with larger pore diameter is used for effective escape of gas generated during product production process. According to production requirements for products, a pore diameter of the third lamination layer can be adjusted to be not larger than that of the first lamination layer. Thus mechanical strength and gas exhaust capacity can be balanced.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A processing device identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field; identifies a second set of bits associated with the translation unit, wherein the second set of bits corresponds to a block field; updates a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value; updates a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number; determines, based on the updated first portion and the updated second portion, that a swapping condition is satisfied; and performs a data access operation on a set of memory cells residing at a location corresponding to the translation unit.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region which includes sub-pixels arranged in array, each sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extends in a first direction and include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row. A layer where the plurality of first reset signal lines are located is different from layers where the plurality of second reset signal lines are located.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. In the display substrate, each signal line includes a first conductive portion; for at least one signal line, the display substrate includes a multi-layer insulating pattern on a side of the first conductive portion of each signal line away from the base substrate, and at least one insulating pattern covers a surface of a side of the first conductive portion away from the base substrate; a first insulating pattern in the multi-layer insulating pattern includes a hollow, and an orthographic projection of the hollow on the base substrate is at least partially in a region surrounded by an orthographic projection of the first conductive portion on the base substrate; and a material of the first insulating pattern includes an organic insulating material.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

Abstract: This application relates to the artificial intelligence (AI) field, and specifically, to a voice quality enhancement method and a related device. The method includes: after a PNR mode is enabled, obtaining a noisy voice signal and target voice-related data, where the noisy-carrying voice signal includes a voice signal of a target user and an interfering noise signal, and the target voice-related data indicates a voice feature of the target user; and performing noise reduction on the noisy voice signal based on the target voice-related data by using a trained voice noise reduction model to obtain a noise-reduced voice signal of the target user, where the voice noise reduction model is implemented based on a neural network. In embodiments of this application, voice of a target person can be enhanced, and interference can be suppressed.

Abstract: Provided is a CD5-targeting fully human antibody or an antigen-binding fragment thereof, which specifically binds to CD5 with a high affinity, has a lower immunogenicity compared to heterologous antibodies, and has a good application potential in the development of antibody drugs, cell therapy drugs, detection reagents and the like.

Abstract: A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 ?, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

Abstract: The present disclosure is directed to methods and devices for devices including multiple die. A wafer is received having a plurality of die and a plurality of scribe lines. A dicing process is performed on the wafer. The dicing process includes identifying a first scribe line of the plurality of scribe lines, the first scribe line interposing a first die and a second die of the plurality of die; and performing a partial cut on the first scribe line. In embodiments, other scribe lines of the wafer are, during the dicing process, fully cut. After the dicing, the first die and the second die are mounted on a substrate such as an interposer. The first die and the second die are connected by a portion of the first scribe line, e.g., remaining from the partial cut, during the mounting.

Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.