Patents by Inventor Meng-Wei Chen
Meng-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8850369Abstract: A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.Type: GrantFiled: April 20, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Hsiang Lung, Kuei-Shun Chen, Meng-Wei Chen, Chia-Ying Lee
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Patent number: 8840796Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.Type: GrantFiled: October 1, 2013Date of Patent: September 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei-Shun Chen, Meng-Wei Chen
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Patent number: 8822343Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.Type: GrantFiled: September 4, 2012Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Wen Hsieh, Chi-Kang Chang, Chia-Chu Liu, Meng-Wei Chen, Kuei-Shun Chen
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Patent number: 8716139Abstract: A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist.Type: GrantFiled: March 1, 2012Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Meng Wei Chen
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Publication number: 20140065832Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.Type: ApplicationFiled: September 4, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Wen Hsieh, Chi-Kang Chang, Chia-Chu Liu, Meng-Wei Chen, Kuei-Shun Chen
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Publication number: 20140024218Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.Type: ApplicationFiled: October 1, 2013Publication date: January 23, 2014Inventors: Chia-Chu Liu, Kuei-Shun Chen, Meng-Wei Chen
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Publication number: 20130280909Abstract: A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Hsiang Lung, Kuei-Shun Chen, Meng-Wei Chen, Chia-Ying Lee
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Patent number: 8562843Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.Type: GrantFiled: October 18, 2011Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei Shun Chen, Meng Wei Chen
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Publication number: 20130230980Abstract: A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George LIU, Kuei Shun CHEN, Meng Wei CHEN
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Patent number: 8455982Abstract: An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.Type: GrantFiled: February 29, 2012Date of Patent: June 4, 2013Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Meng-Wei Chen, Chi-Chuang Lee, Chung-Hsien Lin
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Publication number: 20130095662Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Chu Liu, Kuei Shun Chen, Meng Wei Chen
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Patent number: 8237297Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D1; a second STI feature in the device region and having a second depth D2; an alignment mark with patterned features overlying the first STI in the alignment region; and a gate stack formed on an active region in the device region.Type: GrantFiled: July 13, 2010Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei Shun Chen, Meng-Wei Chen, George Liu, Jiann Yuan Huang, Chia-Ching Lin
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Publication number: 20120153441Abstract: An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.Type: ApplicationFiled: February 29, 2012Publication date: June 21, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Wei Chen, Chi-Chuang Lee, Chung-Hsien Lin
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Patent number: 8203836Abstract: A cover structure is disposed at the electronic device. The electronic device includes a frame with an opening and a power supply. The cover structure includes a cover and a pivotal portion. The cover includes an inner surface, an outer surface, and a touch portion. The pivotal portion includes a pivotal part and a trigger. The pivotal part is located on the inner surface. The trigger is located at the opening of the frame and connected with the pivotal part. The touch portion corresponds to the opening. When the touch portion is pressed, the pivotal part drives the trigger to trigger the power supply to drive the electronic device.Type: GrantFiled: January 29, 2010Date of Patent: June 19, 2012Assignee: Asustek Computer Inc.Inventors: Hsin-Chih Chen, Yun-Chung Chang, Hsin-Chi Huang, Meng-Wei Chen, Li-Wen Hsu, Ju-I Lee
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Patent number: 8148232Abstract: Methods and apparatuses for alignment are disclosed. An exemplary method includes providing a substrate having a device region and an alignment region; forming a first material layer over the substrate; forming a device feature and a dummy feature in the first material layer, wherein the device feature is formed in the device region and the dummy feature is formed in the alignment region; forming a second material layer over the first material layer; and forming an alignment feature in the second material layer, the alignment feature being disposed over the dummy feature in the alignment region. The device feature has a first dimension and the dummy feature has a second dimension, the second dimension being less than a resolution of an alignment mark detector.Type: GrantFiled: August 11, 2010Date of Patent: April 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Wei Chen, Chi-Chuang Lee, Chung-Hsien Lin
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Publication number: 20120038021Abstract: Methods and apparatuses for alignment are disclosed. An exemplary method includes providing a substrate having a device region and an alignment region; forming a first material layer over the substrate; forming a device feature and a dummy feature in the first material layer, wherein the device feature is formed in the device region and the dummy feature is formed in the alignment region; forming a second material layer over the first material layer; and forming an alignment feature in the second material layer, the alignment feature being disposed over the dummy feature in the alignment region.Type: ApplicationFiled: August 11, 2010Publication date: February 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Wei Chen, Chi-Chuang Lee, Chung-Hsien Lin
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Publication number: 20110241119Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D1; a second STI feature in the device region and having a second depth D2; an alignment mark with patterned features overlying the first STI in the alignment region; and a gate stack formed on an active region in the device region.Type: ApplicationFiled: July 13, 2010Publication date: October 6, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei Shun Chen, Meng-Wei Chen, George Liu, Jiann Yuan Huang, Chia-Ching Lin
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Publication number: 20100214731Abstract: A cover structure is disposed at the electronic device. The electronic device includes a frame with an opening and a power supply. The cover structure includes a cover and a pivotal portion. The cover includes an inner surface, an outer surface, and a touch portion. The pivotal portion includes a pivotal part and a trigger. The pivotal part is located on the inner surface. The trigger is located at the opening of the frame and connected with the pivotal part. The touch portion corresponds to the opening. When the touch portion is pressed, the pivotal part drives the trigger to trigger the power supply to drive the electronic device.Type: ApplicationFiled: January 29, 2010Publication date: August 26, 2010Applicant: ASUSTEK COMPUTER INC.Inventors: Hsin-Chih Chen, Yun-Chung Chang, Hsin-Chi Huang, Meng-Wei Chen, Li-Wen Hsu, Ju-I Lee
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Patent number: 7097945Abstract: A method of reducing a critical dimension (“CD”) bias between a dense pattern and an isolation pattern is disclosed. The method includes a first step of providing a mask having a dense pattern, an isolation pattern and the other area of the mask is transparent, in which mask the dense pattern has a first opaque pattern and the isolation pattern has a second opaque pattern. The second step of the method is forming a virtual pattern around the isolation pattern, in which a distance between the virtual pattern and the isolation pattern is y, and the virtual pattern has a pattern line width x. By forming the virtual pattern around the isolation pattern, the flare effect of the isolation pattern is close to that of the dense pattern, thus the CD bias between a dense pattern, and an isolation pattern is reduced, and the process window does not shrink.Type: GrantFiled: April 18, 2003Date of Patent: August 29, 2006Assignee: MACRONIX International Co., Ltd.Inventors: Ching-Yu Chang, Hsin-huei Chen, Meng-Wei Chen
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Publication number: 20050009341Abstract: A method of reducing a critical dimension (“CD”) bias between a dense pattern and an isolation pattern is disclosed. The method includes a first step of providing a mask having a dense pattern, an isolation pattern and the other area of the mask is transparent, in which mask the dense pattern has a first opaque pattern and the isolation pattern has a second opaque pattern. The second step of the method is forming a virtual pattern around the isolation pattern, in which a distance between the virtual pattern and the isolation pattern is y, and the virtual pattern has a pattern line width x. By forming the virtual pattern around the isolation pattern, the flare effect of the isolation pattern is close to that of the dense pattern, thus the CD bias between a dense pattern, and an isolation pattern is reduced, and the process window does not shrink.Type: ApplicationFiled: April 18, 2003Publication date: January 13, 2005Inventors: Ching-Yu Chang, Hsin-Huei Chen, Meng-Wei Chen