Abstract: A system comprises a multi-core silicon-on-chip (SOC) device. The SOC device includes a core module, a test data shift path, a core power control module, and an emulation control module. The core module includes a TAP controller and a plurality of data registers. The test data shift path is operable to transport data shifted out of one or more of the data registers. The core power control module is operable to control the power status of the core module. The emulation control module includes a plurality of alternative registers operable to shift data into the test data shift path in the event that the core module is powered down by the core power control module such that the shift path continues uninterrupted. The emulation control module remains powered on regardless of the power status of the core module.

Abstract: An IEEE 1394 serial bus (58) is interfaced utilizing a physical layer (54) to extract the data and a link/transaction layer controller (200) to interface the data from the physical layer (54) to a host system. The host system consists of a peripheral device (210) which is interfaced with various host buses (202). The link/transaction layer controller (200) is operable to emulate the microcontroller function such that addresses can be transmitted to the peripheral device (210) along with data, such that a remote node can access the peripheral device (210) by transmitting address and data information thereto. Alternatively, address and data information can be transmitted from the peripheral device (210) to the controller (200) which will process the received address and data and transmit it to a remote node.