Abstract: A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device.

Abstract: A power adapter for supplying electrical power to a device includes a processor, an interface for power transfer with the device, a multi-winding feedback converter to receive an AC power input and to convert the AC power input to a DC power output over the interface for the device, and a power conversion control circuit. A voltage level of the DC power output is set based on a reference voltage produced by the processor. The power conversion control circuit receives the reference voltage and a control signal based on the voltage level of the DC power output to generate switch control signals to control switches of the multi-winding feedback converter to control the voltage level of the DC power output. The processor recognizes a load associated with the device and sets, using the reference voltage, the DC power output based on the recognized load.

Abstract: A power adapter for supplying electrical power to a device includes a processor, an interface for power transfer with the device, a multi-winding feedback converter to receive an AC power input and to convert the AC power input to a DC power output over the interface for the device, and a power conversion control circuit. A voltage level of the DC power output is set based on a reference voltage produced by the processor. The power conversion control circuit receives the reference voltage and a control signal based on the voltage level of the DC power output to generate switch control signals to control switches of the multi-winding feedback converter to control the voltage level of the DC power output. The processor recognizes a load associated with the device and sets, using the reference voltage, the DC power output based on the recognized load.

Abstract: A power adapter for supplying electrical power to a mobile device. The power adapter may have a processor and an interface for data communication and power transmission with the mobile device, memory internal to a casing of the power adapter, and an AC/DC power conversion circuit electrically coupled to the processor. The AC/DC power conversion circuit is configured to receive an AC power input and convert the AC power input to a DC power output over the interface for the mobile device. The processor is configured to: recognize a load associated with the mobile device connected to the DC power output; set the DC power output based on the load; receive backup data from the mobile device over the interface; and store the backup data from the mobile device within the memory.

Abstract: An integrated circuit device, such as a system-on-a-chip (SOC) device that includes an integrated or embedded voltage regulator, comprises an integrated capacitor and an integrated inductor having a magnetic core that can be fabricated in the same process as the capacitive structure of the integrated capacitor.

Abstract: An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece.

Abstract: A power adapter for supplying electrical power to a mobile device. The power adapter may have a processor and an interface for data communication and power transmission with the mobile device, memory internal to a casing of the power adapter, and an AC/DC power conversion circuit electrically coupled to the processor. The AC/DC power conversion circuit is configured to receive an AC power input and convert the AC power input to a DC power output over the interface for the mobile device. The processor is configured to: recognize a load associated with the mobile device connected to the DC power output; set the DC power output based on the load; receive backup data from the mobile device over the interface; and store the backup data from the mobile device within the memory.

Abstract: An integrated circuit device, such as a system-on-a-chip (SOC) device that includes an integrated or embedded voltage regulator, comprises an integrated capacitor and an integrated inductor having a magnetic core that can be fabricated in the same process as the capacitive structure of the integrated capacitor.

Abstract: A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device.

Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

Abstract: An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece.

Abstract: Embodiments are provided that include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line. Embodiments of forming the inductor can include: providing an inductor design including a conductive line having at least one turn; determining a region of the conductive line that has current density below a threshold; and forming an opening in the region, the opening enclosed within the conductive line.

Abstract: One or more high-inductance, high-quality factor (Q) three-dimensional inductors, for example, solenoid or toroid inductors with small form factors, are provided in an integrated circuit package, such as an integrated fanout package.

Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.

Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.

Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.

Abstract: Disclosed is a resonator made up of three sections (i.e., first, second and third sections) of a semiconductor layer. The second section has an end abutting the first section, a middle portion (i.e., an inductor portion) coiled around the first section and another end abutting the third section. The first and third sections exhibit a higher capacitance to the wafer substrate than the second section. Also disclosed are a process control system and method that incorporate one or more of these resonators. Specifically, during processing by a processing tool, wireless interrogation unit(s) detect the frequency response of resonator(s) in response to an applied stimulus. The detected frequency response is measured and used as the basis for making real-time adjustments to input settings on the processing tool (e.g., as the basis for making real-time adjustments to the temperature setting(s) of an anneal chamber).

Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.