Abstract: A method for decommissioning a nuclear facility includes: floating the nuclear reactor pressure vessel above the cavity; rotating the reactor pressure vessel so that the upper portion of the nuclear reactor pressure vessel is closer to the bio-protective concrete than the lower portion; mounting the upper portion of the nuclear reactor pressure vessel on the neighboring upper surface of the bio-protective concrete; and cutting and decommissioning the nuclear reactor pressure vessel mounted on the neighboring upper surface.

Abstract: Lithium secondary batteries are disclosed. In an embodiment, a lithium secondary battery includes an anode including an anode active material that includes carbon-based active material particles including carbon, the carbon-based active material particles having a Brunauer-Emmett-Teller (BET) specific surface area of 3.0 m2/g to 5.0 m2/g and an average particle diameter (D50) of 5?m to 7.5 ?m, a cathode facing the anode, and a non-aqueous electrolyte solution including a non-aqueous organic solvent that includes a propionate-based organic solvent including propionate and a lithium salt. A content of the propionate-based organic solvent relative to a total volume of the non-aqueous organic solvent is 55 vol % or more.

Abstract: A memory device includes a fail test circuit configured to generate a fail flag indicating whether a failure was detected in a column line, on the basis of internal data outputted from the column line selected according to a column address, when performing a test, and control the fail flag to indicate that the failure was detected in the column line, on the basis of a fail control signal. The memory device also includes a repair information generation circuit configured to generate, from the column address, a repair column address for repairing the column line, on the basis of the fail flag.

Abstract: A memory device includes a fail test circuit configured to generate a fail flag indicating whether a failure was detected in a column line, on the basis of internal data outputted from the column line selected according to a column address, when performing a test, and control the fail flag to indicate that the failure was detected in the column line, on the basis of a fail control signal. The memory device also includes a repair information generation circuit configured to generate, from the column address, a repair column address for repairing the column line, on the basis of the fail flag.

Abstract: An apparatus includes a potential failure information generation circuit configured to generate potential failure inforrnation by detecting, based on first failure information on a first faded signal line and second failure information on a second faded signal line, whether the first failed signal line and the second faded signal line are adjacent to each other; and a flag generation circuit configured to generate a flag by comparing the potential failure information with redundancy repair information.

Abstract: A memory device includes an at least one first normal mat and an at least one second normal mat, a first redundancy mat configured to provide one or more first redundancy column lines for repairing one or more column lines disposed in the at least one first normal mat, a second redundancy mat configured to provide one or more second redundancy column lines for repairing one or more column lines disposed in the at least one second normal mat, and a redundancy segmented input/output (I/O) line coupled to both of the first redundancy mat and the second redundancy mat.

Abstract: An apparatus includes a potential failure information generation circuit configured to generate potential failure inforrnation by detecting, based on first failure information on a first faded signal line and second failure information on a second faded signal line, whether the first failed signal line and the second faded signal line are adjacent to each other; and a flag generation circuit configured to generate a flag by comparing the potential failure information with redundancy repair information.

Abstract: A memory device includes an at least one first normal mat and an at least one second normal mat, a first redundancy mat configured to provide one or more first redundancy column lines for repairing one or more column lines disposed in the at least one first normal mat, a second redundancy mat configured to provide one or more second redundancy column lines for repairing one or more column lines disposed in the at least one second normal mat, and a redundancy segmented input/output (I/O) line coupled to both of the first redundancy mat and the second redundancy mat.

Abstract: A memory module includes: a plurality of memories, wherein each of the memories comprises: an encryption key storage circuit suitable for storing an encryption key; an address encryption circuit suitable for generating an encrypted address by encrypting an address transferred from a memory controller by using the encryption key stored in the encryption key storage circuit; and a cell array accessed by the encrypted address, wherein the encryption key storage circuits of the memories store different encryption keys.

Abstract: Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.

Abstract: A semiconductor memory device includes a controller for sequentially activating first and second control signals and activating a third control signal during an amplification period, in a pseudo cryogenic temperature, a first driver for driving a first power source line with a first voltage during an initial period of the amplification period, based on the first control signal, a second driver for driving the first power source line with a second voltage during a later period of the amplification period, based on the second control signal, a third driver for driving a second power source line with a third voltage during the amplification period, based on the third control signal, and a sense amplifier for primarily amplifying a voltage difference between a data line pair using the first and third voltages during the initial period, and secondarily amplifying the difference using the second and third voltages during the later period.

Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.

Abstract: Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.

Abstract: A memory module includes: a plurality of memories, wherein each of the memories comprises: an encryption key storage circuit suitable for storing an encryption key; an address encryption circuit suitable for generating an encrypted address by encrypting an address transferred from a memory controller by using the encryption key stored in the encryption key storage circuit; and a cell array accessed by the encrypted address, wherein the encryption key storage circuits of the memories store different encryption keys.

Abstract: A semiconductor memory device includes a controller for sequentially activating first and second control signals and activating a third control signal during an amplification period, in a pseudo cryogenic temperature, a first driver for driving a first power source line with a first voltage during an initial period of the amplification period, based on the first control signal, a second driver for driving the first power source line with a second voltage during a later period of the amplification period, based on the second control signal, a third driver for driving a second power source line with a third voltage during the amplification period, based on the third control signal, and a sense amplifier for primarily amplifying a voltage difference between a data line pair using the first and third voltages during the initial period, and secondarily amplifying the difference using the second and third voltages during the later period.

Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.

Abstract: A data output buffer may be provided. The data output buffer may include a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. The data output buffer may include a pull-up driver configured to output the pull-up drive signal by driving a pull-up signal, and selectively activate the pull-up drive signal based on the pull-up feedback signal. The data output buffer may include a pull-down circuit configured to output a pull-down feedback signal by pull-down driving the output node based on a pull-down drive signal. The data output buffer may include a pull-down driver configured to output the pull-down drive signal by driving a pull-down signal, and selectively activate the pull-down drive signal based on the pull-down feedback signal.

Abstract: A data output buffer may be provided. The data output buffer may include a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. The data output buffer may include a pull-up driver configured to output the pull-up drive signal by driving a pull-up signal, and selectively activate the pull-up drive signal based on the pull-up feedback signal. The data output buffer may include a pull-down circuit configured to output a pull-down feedback signal by pull-down driving the output node based on a pull-down drive signal. The data output buffer may include a pull-down driver configured to output the pull-down drive signal by driving a pull-down signal, and selectively activate the pull-down drive signal based on the pull-down feedback signal.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. The second semiconductor device may repeatedly write and read out data into and from a plurality of memory cells sequentially selected by addresses that are sequentially counted or may repeatedly write and read out the data into and from specific memory cells selected by a specific address among the addresses, according to the clock signal and the command address signals in response to the test mode signal.

Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.