Abstract: A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.

Abstract: A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.

Abstract: Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value. Thus, continuity of output data can be guaranteed, and hardware can be shared by using time assignment algorithm so that a total size of the interpolation filter can be reduced.

Abstract: An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

Abstract: An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N?1)th fragmented delay phases; an adding unit adding each of the first to the (N?1)th fragmented delay phases to the phase error to generate first to (N?1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N?1)th phase errors.

Abstract: The present invention relates to a fused heterocyclic compound having the Formula 1, which is useful as a platelet aggregation inhibitor, a method for preparing the same, and a pharmaceutical composition for inhibiting platelet aggregation comprising the same.

Abstract: An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

Abstract: A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

Abstract: A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

Abstract: An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N?1)th fragmented delay phases; an adding unit adding each of the first to the (N?1)th fragmented delay phases to the phase error to generate first to (N?1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N?1)th phase errors.

Abstract: The present invention relates to a pharmaceutical composition for treating alcohol-induced liver injury comprising (4S,5S)-5-fluoromethyl-5-hydroxy-4-({[(5R)-5-isopropyl-3-(isoquinolin-1-yl)-4,5-dihydro-5-isoxazolyl]carbonyl}amino)-dihydrofuran-2-one or pharmaceutically acceptable salt thereof, and a use thereof.

Abstract: The present invention relates to a pyridazinone derivative which can be used as a caspase inhibitor, process for the preparation thereof, and pharmaceutical composition for inhibiting caspase comprising the same.

Abstract: The present invention relates to a pyridone derivative which can be used as a caspase inhibitor, process for the preparation thereof, and pharmaceutical composition for inhibiting caspase comprising the same.

Abstract: The present invention relates to an isoxazoline derivative as an inhibitor against various caspases, a process for preparing the same, and a therapeutic composition for preventing inflammation and apoptosis comprising the same.

Abstract: The present invention relates to an isoxazoline derivative as an inhibitor against various caspases, a process for preparing the same, and a therapeutic composition for preventing inflammation and apoptosis comprising the same

Abstract: The present invention provides to an isoxazoline derivative of formula (I), the pharmaceutically acceptable salts, esters and stereochemically isomeric forms thereof, and the use of the derivative in inhibiting the activity of caspases. The present invention also provides a pharmaceutical composition for preventing inflammation and apoptosis which comprise the isoxazoline derivative, pharmaceutically acceptable salts, esters and stereochemically isomeric forms thereof and the process for preparing the same. The derivative according to the present invention can be effectively used in treating diseases due to caspases, such as, for example the disease in which cells are abnormally died, dementia, cerebral stroke, AIDS, diabetes, gastric ulcer, hepatic injury by hepatitis, sepsis, organ transplantation rejection reaction and anti-inflammation.