Patents by Inventor Miao-Chun Chung

Miao-Chun Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9231078
    Abstract: A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: January 5, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Miao-Chun Chung, Yin-Fu Huang, Shih-Chin Lien
  • Patent number: 9029947
    Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
  • Publication number: 20150035583
    Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.
    Type: Application
    Filed: October 21, 2014
    Publication date: February 5, 2015
    Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
  • Patent number: 8896061
    Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 25, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
  • Publication number: 20140175526
    Abstract: A semiconductor device where at least one of a portion of the first metal layer that extends from the source contact, a portion of the second metal layer that extends from the source contact, a portion of the first metal layer that extends from the drain contact, and a portion of the second metal layer that extends from the drain contact is configured to lie above a portion of or even all of the gate. Methods of fabricating and using such a semiconductor device are also provided.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuo Hung Hsieh, Meng Shien Hsieh, Yin Fu Huang, Miao Chun Chung
  • Publication number: 20140151764
    Abstract: A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Miao-Chun Chung, Yin-Fu Huang, Shih-Chin Lien
  • Publication number: 20140077866
    Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
  • Patent number: 8643072
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: February 4, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Miao-Chun Chung, An-Li Cheng, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan Wu
  • Publication number: 20140015016
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Miao-Chun Chung, An-Li Cheng, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan Wu
  • Publication number: 20130037883
    Abstract: An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a tightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.
    Type: Application
    Filed: October 10, 2012
    Publication date: February 14, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yin-Fu Huang, Miao-Chun Chung, Shih-Chin Lien
  • Patent number: 8304830
    Abstract: An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a lightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: November 6, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Yin-Fu Huang, Miao-Chun Chung, Shih-Chin Lien
  • Publication number: 20110303977
    Abstract: An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a lightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 15, 2011
    Inventors: Yin-Fu Huang, Miao-Chun Chung, Shih-Chin Lien