Patents by Inventor Miao Xu
Miao Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9960260Abstract: A Metal Oxide Thin Film Transistor (MOTFT) and a preparation method thereof are provided. The preparation method includes the following steps in turn: Step a: a metal conductive layer is prepared and patterned as a gate on a substrate; Step b: a first insulating thin film is deposited as a gate insulating layer on the metal conductive layer; Step c: a metal oxide thin film is deposited and patterned as an active layer on the gate insulating layer; Step d: an organic conductive thin film is deposited as a back channel etch protective layer on the active layer; Step e: a metal layer is deposited on the back channel etch protective layer and then patterned as pattern of a source electrode and a drain electrode; Step f: a second insulating thin film is deposited as a passivation layer on the source electrode and the drain electrode.Type: GrantFiled: August 7, 2013Date of Patent: May 1, 2018Assignee: Guang Zhou New Vision Opto-Electronic Technology Co., Ltd.Inventors: Miao Xu, Dongxiang Luo, Hongmeng Li, Jiawei Pang, Ying Guo, Lang Wang
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Publication number: 20180110798Abstract: The invention provides for methods of treating lysosomal storage disorders and/or reduction of non-cholesterol lipids, using cyclodextrin compounds, including in combination with other therapeutics, including vitamin E.Type: ApplicationFiled: June 12, 2017Publication date: April 26, 2018Inventors: John McKew, Wei Zheng, Miao Xu, Manju Swaroop, Juan J. Marugan
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Publication number: 20180015153Abstract: The present invention concerns the use of compounds for the treatment or prevention of Flavivirus infections, such as Zika virus infections. Aspects of the invention include methods for treating or preventing Flavivirus virus infection, such as Zika virus infection, by administering a compound or class of compound disclosed herein, such as a niclosamide compound, an emricasan compound, a cyclin-dependent kinase inhibitor, a proteasome inhibitor, or a combination of two or more of the foregoing, to a subject in need thereof; methods for inhibiting Flavivirus infections such as Zika virus infections in a cell in vitro or in vivo; pharmaceutical compositions; packaged dosage formulations; and kits for treating or preventing Flavivirus infections, such Zika virus infections.Type: ApplicationFiled: July 14, 2017Publication date: January 18, 2018Inventors: HENGLI TANG, EMILY M. LEE, YICHEN CHENG, YI ZHOU, WEI ZHENG, RUILI HUANG, MIAO XU, WENWEI HUANG, MENGHANG XIA, HONGJUN SONG, GUO-LI MING, ZHEXING WEN
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Publication number: 20180018700Abstract: A method and device for processing promotion information and a system are provided. The method includes that: agreement information and exposure requirements of all promotion information within a preset period are acquired (101); directional delivered targets are determined according to the agreement information and the exposure requirements, and the directional delivered targets are split into multiple non-intersected delivered target sets (102); the promotion information is delivered to users corresponding to the corresponding delivered target sets according to the exposure requirements (103); statistics about social propagation amounts of to the delivered promotion information is made in real time in a delivery process (104); and exposure parameters are corrected according to the social propagation amounts (105), so that delivery of the promotion information is regulated in real time. By the method, the effectiveness and accuracy of delivering the promotion information may be improved.Type: ApplicationFiled: July 7, 2017Publication date: January 18, 2018Inventors: Chuanjiang LUO, Lei XIAO, Dapeng LIU, Lili ZHAO, Peili LV, Xue BAI, Jinjing LIU, Wei XUE, Miao XU, Yang WANG
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Patent number: 9691624Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.Type: GrantFiled: December 14, 2012Date of Patent: June 27, 2017Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Miao Xu, Jun Luo, Chunlong Li, Guilei Wang
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Patent number: 9679962Abstract: There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.Type: GrantFiled: July 30, 2015Date of Patent: June 13, 2017Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Miao Xu, Huilong Zhu, Lichuan Zhao
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Patent number: 9633854Abstract: The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region.Type: GrantFiled: August 2, 2011Date of Patent: April 25, 2017Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Miao Xu, Qingqing Liang
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Publication number: 20160190236Abstract: There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Though-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.Type: ApplicationFiled: July 30, 2015Publication date: June 30, 2016Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Miao XU, Huilong ZHU, Lichuan ZHAO
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Patent number: 9349867Abstract: Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions.Type: GrantFiled: December 4, 2012Date of Patent: May 24, 2016Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Huilong Zhu, Miao Xu, Qingqing Liang, Haizhou Yin
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Publication number: 20160133729Abstract: A Metal Oxide Thin Film Transistor (MOTFT) and a preparation method thereof are provided. The preparation method includes the following steps in turn: Step a: a metal conductive layer is prepared and patterned as a gate on a substrate; Step b: a first insulating thin film is deposited as a gate insulating layer on the metal conductive layer; Step c: a metal oxide thin film is deposited and patterned as an active layer on the gate insulating layer; Step d: an organic conductive thin film is deposited as a back channel etch protective layer on the active layer; Step e: a metal layer is deposited on the back channel etch protective layer and then patterned as pattern of a source electrode and a drain electrode; Step f: a second insulating thin film is deposited as a passivation layer on the source electrode and the drain electrode.Type: ApplicationFiled: August 7, 2013Publication date: May 12, 2016Inventors: Miao XU, Dongxiang LUO, Hongmeng LI, Jiawei PANG, Ying GUO, Lang WANG
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Patent number: 9252280Abstract: The present disclosure discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. The MOSFET includes: a silicon on insulator (SOI) wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate.Type: GrantFiled: November 18, 2011Date of Patent: February 2, 2016Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Miao Xu, Qingqing Liang
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Publication number: 20150325699Abstract: A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack.Type: ApplicationFiled: December 7, 2012Publication date: November 12, 2015Inventors: Huilong Zhu, Miao Xu
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Publication number: 20150294879Abstract: Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin.Type: ApplicationFiled: December 14, 2012Publication date: October 15, 2015Inventors: Huilong Zhu, Miao Xu, Jun Luo, Chunlong Li, Guilei Wang
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Publication number: 20150287828Abstract: A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack.Type: ApplicationFiled: November 26, 2012Publication date: October 8, 2015Inventors: Huilong Zhu, Miao Xu, Haizhou Yin, Qingqing Liang
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Publication number: 20150255609Abstract: Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions.Type: ApplicationFiled: December 4, 2012Publication date: September 10, 2015Inventors: Huilong Zhu, Miao Xu, Qingqing Liang, Haizhou Yin
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Publication number: 20150221769Abstract: An FinFET and a method for manufacturing the same are disclosed. The FinFET comprises: a semiconductor substrate; a stress layer on the semiconductor substrate; a semiconductor fin on the stress layer, the semiconductor fin having two sidewalls extending in its length direction; a gate dielectric on the sidewalls of the semiconductor fin; a gate conductor on the gate dielectric; and a source region and a drain region at two ends of the semiconductor fin, wherein the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin.Type: ApplicationFiled: August 24, 2012Publication date: August 6, 2015Applicant: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Miao Xu
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Publication number: 20150216895Abstract: The invention provides for methods of treating lysosomal storage disorders and/or reduction of non-cholesterol lipids, using cyclodextrin compounds, including in combination with other therapeutics, including vitamin E.Type: ApplicationFiled: August 3, 2013Publication date: August 6, 2015Inventors: John McKew, Wei Zheng, Miao Xu, Manju Swaroop, Juan J. Marugan
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Publication number: 20150200275Abstract: A FinFET with reduced leakage between source and drain regions, and a method for manufacturing the FinFET are disclosed. In one aspect, the method includes forming, on a semiconductor substrate, at least two openings to define a semiconductor fin. The method also includes forming a gate dielectric layer that conformally covers the fin and the openings. The method also includes forming, within the openings, a first gate conductor adjacent to the bottom of the fin. The method also includes forming, within the openings, an insulating isolation layer on the first gate conductor. The method also includes forming a second gate conductor on the fin and on the insulating isolation layer adjacent to the top of the fin. The method also includes forming spacers on sidewalls of the second gate conductor. The method also includes forming a source region and a drain region in the fin.Type: ApplicationFiled: December 29, 2014Publication date: July 16, 2015Inventors: Huilong Zhu, Miao Xu, Qingqing Liang, Haizhou Yin
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Patent number: 9012963Abstract: The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.Type: GrantFiled: November 18, 2011Date of Patent: April 21, 2015Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Qingqing Liang, Miao Xu, Huilong Zhu, Huicai Zhong
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Patent number: 8933512Abstract: The present application discloses a MOSFET and a method for manufacturing the same.Type: GrantFiled: August 12, 2011Date of Patent: January 13, 2015Assignee: Institute of Microelectronics, Chinese Academy of ScienceInventors: Huilong Zhu, Miao Xu, Qingqing Liang