Abstract: A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay.

Abstract: A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay.

Abstract: A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.

Abstract: A method and apparatus for providing frequency acquisition and locking detection for a phase lock loop is disclosed. The phase lock loop locks a receiver local oscillator to the frequency and phase of an RF carrier to allow data to be recovered from the RF carrier in the receiver. An analog mixer in the phase lock loop compares the frequency and phase of a receive LO output by a voltage controlled oscillator in the phase lock loop and the received RF carrier. A locking indicator dependent on the result of the comparison indicates whether the phase lock loop is locked. The locking indicator is coupled to a comparator. The comparator generates a pulse to close a switch in order to inject a periodic sweeping signal generated by a free running multi vibrator into the phase lock loop to push the receiver LO into the locking range.

Abstract: A differential slicer circuit includes a plurality of differential comparators and threshold voltages. Each differential comparator includes two matched amplifiers cross-coupled as a subtractor for a differential threshold signal dependent on the threshold voltages. The differential comparator outputs a differential output voltage dependent on the difference between an input differential signal and the differential threshold voltage.

Abstract: An automatic gain control circuit in a receiver estimates an AGC gain using information from an estimated amplitude signal derived from a received signal before a carrier signal is recovered from the received signal. The carrier signal is recovered from the received signal using the estimated AGC gain. After the carrier signal is recovered, the amplitude of the estimated amplitude signal decreases below the amplitude of the recovered carrier signal. The Automatic Gain Control circuit uses the amplitude of the recovered I and/or Q signal to accurately set the AGC gain.

Abstract: A ping-pong scheme is used to slow down data transfer speed between an analog slicer in a receiver and a digital physical layer device, while maintaining the same data throughout. Two edges of a clock are used to slice the incoming analog signal, convert the analog signal to a digital signal and latch the converted signal. A ping-pong data pipeline is provided from the analog slicer to the physical layer device.

Abstract: A bandpass delta-sigma modulator converts a signal of a nominal frequency to an oversampled digital signal. Digital decimation filter decimates the signal by multiplying the signal by first and second modulating signals. The modulating signals are selected to have a frequency which can produce a baseband signal with a nominal frequency of &pgr;*/3. By using an oversampling rate of 6 times the carrier frequency signal rate, the modulation signal of a frequency &pgr;*/3 produces a real and imaginary signal. The real and imaginary signal can be filtered in first and second filtering decimation circuits reducing the number of signal processing paths for the signal. The decimated signal is further filtered and decimated using conventional digital filtering techniques.

Abstract: A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.

Abstract: By sampling at six times the carrier frequency cosine and sine multiplication circuits are found to be constructable from simple shift and inversion circuit. Shifting and inversion are controlled by means of a simple finite state machine or other circuits cycling through a six cycle periodic sequence.

Abstract: A programmable gain delta sigma analog-to-digital converter includes an analog input terminal receiving an analog input voltage, a charge summing conductor, an input capacitive switching circuit, and a feedback reference capacitive switching circuit coupled to the charge summing conductor. An integrator is coupled between the charge summing conductor and a comparator which supplies a stream of digital pulses to a digital filter that produces a digital number representing the analog input voltage. The feedback reference capacitive switching circuit includes a plurality of reference sampling capacitors, selectively coupling charge between a feedback reference voltage source and an integrating capacitor of the integration in response to a programmable gain control circuit so as to provide a selected gain for the analog-to-digital converter. The sampling rate of the capacitive switching circuits is adjusted proportionally to the selected gain to improve the dynamic range of the analog-to-digital converter.

Abstract: A switched capacitor input sampling circuit in a chopper stabilized delta sigma modulator includes first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to first and second charge summing conductors, respectively, of the delta sigma modulator.

Abstract: Programmable resolution/bias current control circuitry is provided in a delta sigma analog-to-digital converter including an input sampling circuit, a feedback reference sampling circuit, an integrator including an operational amplifier, a comparator, and a digital filter, the input sampling circuit and the feedback reference sampling circuit being coupled to a first input of the operational amplifier, an output of the operational amplifier being coupled to an input of the comparator, an output of the comparator being coupled to an input of the digital filter. The programmable resolution/bias control circuitry includes a clock generator circuit supplying a clock signal to the input sampling circuit and the feedback sampling circuit at a sampling frequency determined by a sampling frequency control signal. A bias current generator circuit supplies a bias current to the operational amplifier to control the settling time of an output step voltage signal produced by the operational amplifier.