Patents by Inventor Micha Gutman
Micha Gutman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230238070Abstract: A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.Type: ApplicationFiled: March 14, 2023Publication date: July 27, 2023Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.Inventors: Hiroshige HIRANO, Hiroaki KURIYAMA, Masahiko SAKAGAMI, Micha GUTMAN, Erez SARIG, Yakov ROIZIN
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Patent number: 9379194Abstract: A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e.Type: GrantFiled: November 9, 2014Date of Patent: June 28, 2016Assignee: Tower Semiconductor Ltd.Inventors: Micha Gutman, Yakov Roizin, Allon Parag, Vladislav Dayan
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Publication number: 20160133713Abstract: A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e.Type: ApplicationFiled: November 9, 2014Publication date: May 12, 2016Inventors: Micha Gutman, Yakov Roizin, Allon Parag, Vladislav Dayan
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Patent number: 9082867Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).Type: GrantFiled: January 31, 2013Date of Patent: July 14, 2015Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Vladislav Dayan, Micha Gutman
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Publication number: 20150162369Abstract: Solid state radiation sensors include a floating gate (FG) structure having a large control capacitor region disposed on thick dielectric portion over a control gate (CG) implemented by an isolated P-well region, and a tunneling capacitor region disposed on thin gate oxide dielectric over another tunneling gate (TG) isolated P-well region. Opposite voltages (e.g., +5V/?5V) are respectively applied to the CG and TG P-well regions to charge the FG structure by Fowler-Nordheim tunneling. During exposure, radiation striking the sensor discharges the FG structure by generating electron-hole pairs in the dielectric portion separating the CG P-well region and the control capacitor region. After exposure, the total ionizing dose (TID) is calculated, e.g., by measuring the threshold voltage shift of a CMOS readout inverter controlled by the residual charge stored on the FG structure. Sensor performance is enhanced by metal plates, utilizing two control capacitors, or modifying the FG electrode layout.Type: ApplicationFiled: December 9, 2013Publication date: June 11, 2015Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Vladislav Dayan, Micha Gutman
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Publication number: 20140209994Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Vladislav Dayan, Micha Gutman
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Patent number: 8722496Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell production method for CMOS ICs, where the CEONOS NVM cell requires two or three additional masks, but can otherwise be formed using the same standard CMOS flow processes used to form NMOS transistors. A first additional mask is used to form an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data (i.e., trapped charges). A second additional mask is used to perform drain engineering, including a special pocket implant and LDD extensions, which facilitates program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).Type: GrantFiled: January 31, 2013Date of Patent: May 13, 2014Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Evgeny Pikhay, Alexey Heiman, Micha Gutman
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Patent number: 8344440Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.Type: GrantFiled: January 21, 2011Date of Patent: January 1, 2013Assignee: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Micha Gutman, Yakov Roizin
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Publication number: 20110121379Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.Type: ApplicationFiled: January 21, 2011Publication date: May 26, 2011Applicant: Tower Semiconductor Ltd.Inventors: Evgeny Pikhay, Micha Gutman, Yakov Roizin
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Patent number: 7439575Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.Type: GrantFiled: February 23, 2005Date of Patent: October 21, 2008Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Efraim Aloni, Micha Gutman, Menachem Vofsy, Avi Ben-Gigi
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Patent number: 7060627Abstract: A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.Type: GrantFiled: September 9, 2003Date of Patent: June 13, 2006Assignee: Tower Semiconductor Ltd.Inventors: Micha Gutman, Yakov Roizin, Menachem Vofsy, Efraim Aloni, Avi Ben-Gigi, Fumihiko Noro, Masatoshi Arai, Nobuyoshi Takahashi, Koji Yoshida
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Patent number: 7016225Abstract: A non-volatile memory cell capable of storing more than two bits of information. The NVM cell includes a semiconductor region having a first conductivity type, and a plurality of field isolation regions located in the semiconductor region. Four or more source/drain regions are located in the semiconductor region adjacent to the field isolation regions, the source/drain regions having a second conductivity type, opposite the first conductivity type. The field isolation regions and the source drain regions laterally surround a channel region in the semiconductor region. A gate structure, including a floating gate structure and a control gate structure, extends over the channel region, portions of the field isolation regions and portions of the source/drain regions. The floating gate structure includes a plurality of charge trapping regions, wherein each of the charge trapping regions is located adjacent to a corresponding one of the source/drain regions.Type: GrantFiled: November 26, 2002Date of Patent: March 21, 2006Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Micha Gutman, Shimon Greenberg, Alfred Yankelevich
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Patent number: 6959920Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.Type: GrantFiled: September 9, 2003Date of Patent: November 1, 2005Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Efraim Aloni, Micha Gutman, Menachem Vofsy, Avi Ben-Gigi
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Publication number: 20050139903Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.Type: ApplicationFiled: February 23, 2005Publication date: June 30, 2005Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Efraim Aloni, Micha Gutman, Menachem Vofsy, Avi Ben-Gigi
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Publication number: 20050051838Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.Type: ApplicationFiled: September 9, 2003Publication date: March 10, 2005Inventors: Yakov Roizin, Efraim Aloni, Micha Gutman, Menachem Vofsy, Avi Ben-Gigi
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Publication number: 20050054161Abstract: A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.Type: ApplicationFiled: September 9, 2003Publication date: March 10, 2005Inventors: Micha Gutman, Yakov Roizin, Menachem Vofsy, Efraim Aloni, Avi Ben-Gigi, Fumihiko Noro, Masatoshi Arai, Nobuyoshi Takahashi, Koji Yoshida
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Publication number: 20040100822Abstract: A non-volatile memory cell capable of storing more than two bits of information. The NVM cell includes a semiconductor region having a first conductivity type, and a plurality of field isolation regions located in the semiconductor region. Four or more source/drain regions are located in the semiconductor region adjacent to the field isolation regions, the source/drain regions having a second conductivity type, opposite the first conductivity type. The field isolation regions and the source drain regions laterally surround a channel region in the semiconductor region. A gate structure, including a floating gate structure and a control gate structure, extends over the channel region, portions of the field isolation regions and portions of the source/drain regions. The floating gate structure includes a plurality of charge trapping regions, wherein each of the charge trapping regions is located adjacent to a corresponding one of the source/drain regions.Type: ApplicationFiled: November 26, 2002Publication date: May 27, 2004Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Micha Gutman, Shimon Greenberg, Alfred Yankelevich