Abstract: Substrate material is oxidized around side walls of a set of channels. A shielding structure means there is more oxide growth at the top than the bottom with the result that the non-oxidized substrate material area between the channels forms a tapered shape with a pointed tip at the top. These pointed substrate areas are then used to form cathodes.

Abstract: The invention provides a method of forming an electric field gap device, such as a lateral field emission ESD protection structure, in which a cathode layer is formed between dielectric layers. Anode channels are formed and they are lined with a sacrificial dielectric layer. Conductive anode pillars are formed in the anode channels, and then the sacrificial dielectric layer is etched away in the vicinity of the anode pillars. The etching leaves a suspended portion of the cathode layer which defines a lateral gap to an adjacent anode pillar. This portion has a sharp end face defined by the corners of the cathode layer and the lateral gap can be defined accurately as it corresponds to the thickness of the sacrificial dielectric layer.

Abstract: Embodiments of a method for forming a field emission diode for an electrostatic discharge device include forming a first electrode, a sacrificial layer, and a second electrode. The sacrificial layer separates the first and second electrodes. The method further includes forming a cavity between the first and second electrode by removing the sacrificial layer. The cavity separates the first and second electrodes. The method further includes depositing an electron emission material on at least one of the first and second electrodes through at least one access hole after formation of the first and second electrodes. The access hole is located remotely from a location of electron emission on the first and second electrode.

Abstract: Embodiments of a method for forming a field emission diode for an electrostatic discharge device include forming a first electrode, a sacrificial layer, and a second electrode. The sacrificial layer separates the first and second electrodes. The method further includes forming a cavity between the first and second electrode by removing the sacrificial layer. The cavity separates the first and second electrodes. The method further includes depositing an electron emission material on at least one of the first and second electrodes through at least one access hole after formation of the first and second electrodes. The access hole is located remotely from a location of electron emission on the first and second electrode.

Abstract: Substrate material is oxidised around side walls of a set of channels. A shielding structure means there is more oxide growth at the top than the bottom with the result that the non-oxidised substrate material area between the channels forms a tapered shape with a pointed tip at the top. These pointed substrate areas are then used to form cathodes.

Abstract: The invention provides a method of forming an electric field gap device, such as a lateral field emission ESD protection structure, in which a cathode layer is formed between dielectric layers. Anode channels are formed and they are lined with a sacrificial dielectric layer. Conductive anode pillars are formed in the anode channels, and then the sacrificial dielectric layer is etched away in the vicinity of the anode pillars. The etching leaves a suspended portion of the cathode layer which defines a lateral gap to an adjacent anode pillar. This portion has a sharp end face defined by the corners of the cathode layer and the lateral gap can be defined accurately as it corresponds to the thickness of the sacrificial dielectric layer.

Abstract: An electric device has an electrically switchable resistor (2?) comprising a phase change material. The resistance value of the resistor can be changed between at least two values by changing the phase of the phase change material within a part of the resistor called the switching zone (12?) using Joule heating of the resistor. The device comprises a body (24?) encapsulating the resistor, which body comprises at least two abutting regions (26?, 28?) having different thermally insulating properties. These regions form a thermally insulating contrast with which the dimension of the switching zone can be determined without having to alter the dimensions of the resistor. Such a device can be used in electronic memory or reconfigurable logic circuits.

Abstract: A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at the base of the trenches which join up and then filling the trenches with conductor (30).

Abstract: A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.

Abstract: An electric device has an electrically switchable resistor (2?) comprising a phase change material. The resistance value of the resistor can be changed between at least two values by changing the phase of the phase change material within a part of the resistor called the switching zone (12?) using Joule heating of the resistor. The device comprises a body (24?) encapsulating the resistor, which body comprises at least two abutting regions (26?, 28?) having different thermally insulating properties. These regions form a thermally insulating contrast with which the dimension of the switching zone can be determined without having to alter the dimensions of the resistor. Such a device can be used in electronic memory or reconfigurable logic circuits.

Abstract: A phase change resistor device has a phase change material (PCM) for which the phase transition occurs inside the PCM and not at the interface with a contact electrode. For ease of manufacturing the PCM is an elongate line structure (210, 215) surrounded by the conductive electrode portions (200, 240) at its lateral sides, and is formed in a CMOS backend process. An alternative is to form the device coupled directly to other circuit parts without the electrodes. In each case, there is a line of PCM which has a constant diameter or cross section, formed with reduced dimensions by using a spacer as a hard mask. The first contact electrode and the second contact electrode are electrically connected by a “one dimensional” layer of the PCM. The contact resistance between the one-dimensional layer of PCM and the first contact electrode at the second contact electrode is lower than the resistance of a central or intervening portion of the line.

Abstract: A trench-gate transistor (1) has an integral first layer of silicon dioxide (31) which extends from the upper surface (10a) of the semiconductor body (10) over top corners of each cell array trench (20), the integral first layer also providing a thin gate dielectric insulating layer (31A) for a thick gate electrode (41) and the integral first layer also providing a first part (31B) of a stack of materials which constitute a thick trench sidewall insulating layer (31B,32,33) for a thin field plate (42), a layer of silicon nitride (32) providing a second part of the stack and a second layer of silicon dioxide (33) providing a third part of the stack. The integrity of the first silicon dioxide layer (31) over the trench (20) top corners helps to avoid gate (41) source (24) short circuits. In a method of manufacture (FIGS.

Abstract: A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.

Abstract: A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick gate electrode and the integral first layer also provides a first part of a stack of materials which constitute a thick trench sidewall insulating layer for a thin field plate. Consistent with an example embodiment, there is a method of manufacture. A hardmask used to etch the trenches is removed before providing the silicon dioxide layer. The layer is then protected by successive selective etching of the oxide layer and the nitride layer in the upper parts of the trenches. After the gate electrodes are provided, layers for the channel accommodating regions and source regions may be formed through the oxide layer on the upper surface.

Abstract: A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation (21) in the trenches such that the gate insulation (33) at the trench bottoms is thicker than the gate insulation (21) at the trench sidewalls in order to reduce the gate-drain capacitance of the device.

Abstract: A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at the base of the trenches which join up and then filling the trenches with conductor (30).

Abstract: A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.

Abstract: A trench-gate transistor (1) has an integral first layer of silicon dioxide (31) which extends from the upper surface (10a) of the semiconductor body (10) over top corners of each cell array trench (20), the integral first layer also providing a thin gate dielectric insulating layer (31A) for a thick gate electrode (41) and the integral first layer also providing a first part (31B) of a stack of materials which constitute a thick trench sidewall insulating layer (31B,32,33) for a thin field plate (42), a layer of silicon nitride (32) providing a second part of the stack and a second layer of silicon dioxide (33) providing a third part of the stack. The integrity of the first silicon dioxide layer (31) over the trench (20) top corners helps to avoid gate (41)—source (24) short circuits. In a method of manufacture (FIGS.

Abstract: A trench-gate semiconductor device (100) has a trench network (STR1, ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16 which is a section view along the line II-II of FIG. 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100).

Abstract: A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.