Patents by Inventor Michael A. Ashburn, Jr.
Michael A. Ashburn, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10855299Abstract: Described herein are DACs with low distortion for high dynamic range (HDR), extremely high dynamic range (EHDR), and other suitable applications. Some embodiments relate to a device including a DAC configured for coupling to an amplifier via a force path and a sense path. For example, the DAC may provide output current to the amplifier via the force path, and the DAC may sense the input voltage of the amplifier via the sense path. Accordingly, distortion such as harmonic distortion and/or gain offset from parasitic impedances in the force and/or sense paths may be reduced or eliminated. Some embodiments relate to a DAC including a voltage reference generator configured to compensate for variations in impedances of the DAC, such as due to semiconductor process variation. Accordingly, distortion in the DAC output due to variations in the DAC impedances may be reduced or eliminated.Type: GrantFiled: August 29, 2019Date of Patent: December 1, 2020Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Ayman Shabra, Michael A Ashburn, Jr., Patrick Cooney, Adalberto Cantoni, Joshua M. Bamford
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Patent number: 10833697Abstract: Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.Type: GrantFiled: September 3, 2019Date of Patent: November 10, 2020Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Ayman Shabra, Stacy Ho, Michael A. Ashburn, Jr.
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Publication number: 20200112317Abstract: Described herein are DACs with low distortion for high dynamic range (HDR), extremely high dynamic range (EHDR), and other suitable applications. Some embodiments relate to a device including a DAC configured for coupling to an amplifier via a force path and a sense path. For example, the DAC may provide output current to the amplifier via the force path, and the DAC may sense the input voltage of the amplifier via the sense path. Accordingly, distortion such as harmonic distortion and/or gain offset from parasitic impedances in the force and/or sense paths may be reduced or eliminated. Some embodiments relate to a DAC including a voltage reference generator configured to compensate for variations in impedances of the DAC, such as due to semiconductor process variation. Accordingly, distortion in the DAC output due to variations in the DAC impedances may be reduced or eliminated.Type: ApplicationFiled: August 29, 2019Publication date: April 9, 2020Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: Ayman Shabra, Michael A. Ashburn, JR., Patrick Cooney, Adalberto Cantoni, Joshua M. Bamford
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Publication number: 20200083900Abstract: Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.Type: ApplicationFiled: September 3, 2019Publication date: March 12, 2020Applicant: MEDIATEK Singapore Pte. Ltd.Inventors: Ayman Shabra, Stacy Ho, Michael A. Ashburn, JR.
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Patent number: 10476456Abstract: A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.Type: GrantFiled: March 22, 2017Date of Patent: November 12, 2019Assignee: MediaTek Inc.Inventors: Ayman Shabra, Michael A. Ashburn, Jr.
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Patent number: 10075181Abstract: According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.Type: GrantFiled: September 13, 2017Date of Patent: September 11, 2018Assignee: MediaTek Inc.Inventors: Sheng-Jui Huang, Nathan Egan, Divya Kesharwani, Michael A. Ashburn, Jr., Frank Op 't Eynde
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Patent number: 10075180Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.Type: GrantFiled: November 10, 2017Date of Patent: September 11, 2018Assignee: MediaTek Inc.Inventors: Tao He, Michael A. Ashburn, Jr.
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Publication number: 20180212617Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.Type: ApplicationFiled: November 10, 2017Publication date: July 26, 2018Inventors: Tao He, Michael A. Ashburn, JR.
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Publication number: 20180212618Abstract: Circuits for compensating delta-sigma modulators for excess loop delay are described. These circuits may be coupled to quantizers, and may configured to select the threshold values supplied to the quantizers for comparison with an analog signal. The threshold values may each be selected from a corresponding plurality of reference values, and may be set such that the numerical order of threshold values varies over time. For example, the threshold value provided to a first comparator of the quantizer may be greater than the threshold value provided to a second comparator of the quantizer in a first time interval, but the opposite scenario may occur in a second time interval. The circuits may include multiplexers for selecting the threshold values, thermometric encoders, reference selectors and reference multiplexers.Type: ApplicationFiled: January 19, 2018Publication date: July 26, 2018Inventors: Tao He, Michael A. Ashburn, JR.
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Publication number: 20180097487Abstract: A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.Type: ApplicationFiled: March 22, 2017Publication date: April 5, 2018Applicant: MediaTek Inc.Inventors: Ayman Shabra, Michael A. Ashburn, JR.
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Publication number: 20180006661Abstract: According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.Type: ApplicationFiled: September 13, 2017Publication date: January 4, 2018Inventors: Sheng-Jui Huang, Nathan Egan, Divya Kesharwani, Michael A. Ashburn, JR., Frank Op 't Eynde
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Publication number: 20170194984Abstract: A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.Type: ApplicationFiled: March 17, 2017Publication date: July 6, 2017Inventors: Sheng-Jui Huang, Michael A. Ashburn, JR., Divya Kesharwani, Nathan Egan
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Patent number: 9634687Abstract: A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.Type: GrantFiled: March 14, 2016Date of Patent: April 25, 2017Assignee: MEDIATEK INC.Inventors: Sheng-Jui Huang, Michael A. Ashburn, Jr., Divya Kesharwani, Nathan Egan
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Publication number: 20160365870Abstract: A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.Type: ApplicationFiled: March 14, 2016Publication date: December 15, 2016Inventors: Sheng-Jui Huang, Michael A. Ashburn, JR., Divya Kesharwani, Nathan Egan
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Patent number: 9461660Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency response modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency response compensator coupled to the frequency response modifier, wherein the frequency response compensator compensates for the modification introduced by the frequency response modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency response compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.Type: GrantFiled: November 11, 2015Date of Patent: October 4, 2016Assignee: MEDIATEK INC.Inventors: Khurram Muhammad, Chi-Lun Lo, Frank Op 't Eynde, Michael A. Ashburn, Jr., Tien-Yu Lo
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Publication number: 20160211856Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency compensator coupled to the frequency modifier, wherein the frequency compensator compensates for the modification introduced by the frequency modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.Type: ApplicationFiled: November 11, 2015Publication date: July 21, 2016Inventors: Khurram MUHAMMAD, Chi-Lun LO, Frank OP 'T EYNDE, Michael A. ASHBURN, JR., Tien-Yu LO
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Patent number: 8653869Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.Type: GrantFiled: September 13, 2012Date of Patent: February 18, 2014Assignee: Media Tek Singapore Pte. Ltd.Inventors: Tsung-Kai Kao, Che-Fu Liang, Michael A. Ashburn, Jr.
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Patent number: 8570200Abstract: An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal.Type: GrantFiled: December 25, 2011Date of Patent: October 29, 2013Assignee: MediaTek Singapore Pte. Ltd.Inventors: Michael A. Ashburn, Jr., Jeffrey Carl Gealow, Paul F. Ferguson, Jr.
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Patent number: 8570201Abstract: A continuous-time sigma-delta analog-to-digital converter includes a plurality of integrator stages, in which one of the integrator stages includes a current buffer that drives an integrating capacitor. The analog-to-digital converter includes an outer feedback digital-to-analog converter and an inner digital-to-analog converter. The inner digital-to-analog converter is a current-mode digital-to-analog converter that converts the digital output signal to an analog current feedback signal, which is provided to an output of the integrator stage that includes the current buffer. Both the analog current feedback signal and an input signal provided to the current buffer are integrated by the integrating capacitor.Type: GrantFiled: January 20, 2012Date of Patent: October 29, 2013Assignee: MediaTek Singapore Pte. Ltd.Inventors: Michael A. Ashburn, Jr., Ayman Shabra
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Publication number: 20130241915Abstract: A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuitsType: ApplicationFiled: April 29, 2013Publication date: September 19, 2013Applicant: ANALOG DEVICES, INC.Inventors: Abhishek BANDYOPADHYAY, Eric G. NESTLER, Michael A. ASHBURN, JR.