Patents by Inventor Michael A. Blake
Michael A. Blake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8763979Abstract: The vehicle seat latch (16) disclosed includes an elongate pivot plate (32) pivotally mounted by a first pivotal connection (36) on a seat frame (28) by a mounting plate (26). A second pivotal connection (42) mounts a latch assembly (40) on the pivot plate (32). The latch assembly (40) includes a throat plate (46) having a throat (48) for receiving a vehicle body mounted striker (24), and the latch assembly (40) also includes at least one latch member (50, 52) movable between latched and unlatched positions for securing the latch to the striker (24). Pivoting of the pivot plate (32) about the first pivotal connection (36) and pivoting of the throat plate (46) about the second pivotal connection (42) provide the latch assembly with compliance that accommodates for striker position variation along transverse directions, which are vertical and horizontal when the seat is latched to the vehicle floor.Type: GrantFiled: May 23, 2012Date of Patent: July 1, 2014Assignee: Porter Group, LLCInventors: Michael A. Blake, Sobieslaw W. Derbis
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Patent number: 8762651Abstract: Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.Type: GrantFiled: June 23, 2010Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Michael A. Blake, Garrett M. Drapala, Pak-Kin Mak, Vesselina K. Papazova, Craig R. Walters
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Publication number: 20140170006Abstract: A compressor assembly is provided and may include a compression cylinder and a compression piston disposed within the compression cylinder that compresses a vapor disposed within the compression cylinder from a suction pressure to a discharge pressure. The compressor assembly may additionally include a crankshaft that cycles the compression piston within the compression cylinder and an injection port in fluid communication with the compression cylinder that selectively communicates intermediate-pressure vapor at a pressure between the suction pressure vapor and the discharge pressure vapor to the compression cylinder. The injection port may communicate the intermediate-pressure vapor to the compression cylinder when the compression piston exposes the injection port and may be prevented from communicating the intermediate-pressure vapor to the compression cylinder when the compression piston blocks the injection port.Type: ApplicationFiled: December 18, 2013Publication date: June 19, 2014Applicant: EMERSON CLIMATE TECHNOLOGIES, INC.Inventors: Ernest R. BERGMAN, John P. ELSON, Frank S. WALLIS, Brian G. SCHROEDER, Michael R. SCHULTZ NAVARA, Adam Michael BLAKE
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Patent number: 8719618Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.Type: GrantFiled: June 13, 2012Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh
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Publication number: 20140095926Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.Type: ApplicationFiled: December 11, 2013Publication date: April 3, 2014Applicant: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh
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Patent number: 8688880Abstract: Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.Type: GrantFiled: June 23, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Garrett M. Drapala, Michael A. Blake, Timothy C. Bronson, Lawrence D. Curley
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Publication number: 20140082289Abstract: Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.Type: ApplicationFiled: November 21, 2013Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh, Kenneth D. Klapproth, Pak-Kin Mak, Vesselina K. Papazova
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Patent number: 8645642Abstract: Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.Type: GrantFiled: June 23, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Michael A. Blake, Pak-kin Mak, Michael F. Fee, Mark S. Farrell
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Publication number: 20130339609Abstract: Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.Type: ApplicationFiled: March 11, 2013Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Michael A. Blake, Craig R. Walters, Pak-Kin Mak
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Publication number: 20130339623Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.Type: ApplicationFiled: January 22, 2013Publication date: December 19, 2013Applicant: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Michael A. Blake, Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Arthur J. O'Neill
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Publication number: 20130339808Abstract: Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.Type: ApplicationFiled: June 14, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Michael A. Blake, Michael Fee, Hieu T. Huynh, Patrick J. Meaney, Arthur J. O'Neill
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Publication number: 20130339608Abstract: Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Michael A. Blake, Craig R. Walters, Pak-Kin Mak
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Publication number: 20130339785Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh
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Publication number: 20130339809Abstract: Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses.Type: ApplicationFiled: March 7, 2013Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Michael A. Blake, Michael Fee, Hieu T. Huynh, Patrick J. Meaney, Arthur J. O'Neill
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Publication number: 20130339622Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.Type: ApplicationFiled: June 14, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekaterina M. Ambroladze, Michael Blake, Tim Bronson, Garrett Drapala, Pak-kin Mak, Arthur J. O'Neill
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Publication number: 20130339613Abstract: Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Pak-Kin Mak, Timothy C. Bronson, Hieu T. Huynh, Kenneth D. Klapproth, Vesselina K. Papazova
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Publication number: 20130313395Abstract: The vehicle seat latch (16) disclosed includes an elongate pivot plate (32) pivotally mounted by a first pivotal connection (36) on a seat frame (28) by a mounting plate (26). A second pivotal connection (42) mounts a latch assembly (40) on the pivot plate (32). The latch assembly (40) includes a throat plate (46) having a throat (48) for receiving a vehicle body mounted striker (24), and the latch assembly (40) also includes at least one latch member (50, 52) movable between latched and unlatched positions for securing the latch to the striker (24). Pivoting of the pivot plate (32) about the first pivotal connection (36) and pivoting of the throat plate (46) about the second pivotal connection (42) provide the latch assembly with compliance that accommodates for striker position variation along transverse directions, which are vertical and horizontal when the seat is latched to the vehicle floor.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Applicant: PORTER GROUP, LLCInventors: Michael A. Blake, Sobieslaw W. Derbis
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Patent number: 8560891Abstract: A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining.Type: GrantFiled: October 18, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh, Pak-kin Mak
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Patent number: 8523262Abstract: A vehicle seat rear floor latch and positioner assembly (22) for a vehicle seat (10) movable between a seating position, a generally horizontal nonuse position, and a generally vertical storage position as well as being removable from the vehicle to increase cargo capacity.Type: GrantFiled: March 21, 2011Date of Patent: September 3, 2013Assignee: Porter Group, LLCInventors: Robert L. Haeske, Michael A. Blake, Brent C. Everett
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Patent number: 8423736Abstract: Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.Type: GrantFiled: June 16, 2010Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Michael A. Blake, Garrett M. Drapala, Pak-Kin Mak, Vesselina K. Papazova, Craig R. Walters