Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

Abstract: There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a semiconductor on insulator (SOI) substrate including a diode and an insulator layer. The composite semiconductor device also includes a transition body formed over the diode, and a transistor formed over the transition body. The diode is connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two.

Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer.

Abstract: A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N+ III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate.

Abstract: A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N+ III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate.

Abstract: A III-nitride semiconductor device which includes a charged floating gate electrode.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: There are disclosed herein various implementations of a method and system for ion implantation at high temperature surface equilibrium conditions. The method may include situating a III-Nitride semiconductor body in a surface equilibrium chamber, establishing a gas pressure greater than or approximately equal to a surface equilibrium pressure of the III-Nitride semiconductor body, and heating the III-Nitride semiconductor body to an elevated implantation temperature in the surface equilibrium chamber while substantially maintaining the gas pressure. The method also includes implanting the III-Nitride semiconductor body in the surface equilibrium at the elevated implantation temperature chamber while substantially maintaining the gas pressure, the implanting being performed using an ion implanter interfacing with the surface equilibrium chamber.

Abstract: A high voltage switching circuit includes first and second group III-V transistors, the second group III-V transistor having a greater breakdown voltage than the first group III-V transistor. The circuit further includes a silicon diode in a parallel arrangement with the first group III-V transistor, the parallel arrangement being in cascade with the second group III-V transistor. The circuit is effectively a three-terminal device, where a first terminal is coupled to a gate of the second III-V transistor, a source of the first III-V transistor, and an anode of the silicon diode. A second terminal is coupled to a gate of the first group III-V transistor, and a third terminal is coupled to a drain of the second group III-V transistor. The first group III-V transistor might be an enhancement mode transistor. The second group III-V transistor might be a depletion mode transistor. The first and second group III-V transistors can be GaN HEMTs.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method.

Abstract: In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can be situated over the group IV transistor die.

Abstract: There are disclosed herein various implementations of a group III-V device including a shield plate. Such a group III-V device includes a substrate, a transition body situated over the substrate, a device channel layer situated over the transition body, and a device barrier layer situated over the device channel layer and producing a device two-dimensional electron gas (2-DEG). The group III-V device also includes a drain electrode coupled to the device barrier layer, and a shield plate, which may be coupled to the drain electrode or may be a floating shield plate. The shield plate is configured to substantially shield the device 2-DEG from charge centers situated over the device barrier layer.

Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

Abstract: According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.

Abstract: There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a transition body formed over a diode, the transition body including more than one semiconductor layer. The composite semiconductor device also includes a transistor formed over the transition body. The diode may be connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two.

Abstract: There are disclosed herein various implementations of a monolithically integrated component. In one exemplary implementation, such a monolithically integrated component includes an enhancement mode group IV transistor and two or more depletion mode III-Nitride transistors. The enhancement mode group IV transistor may be implemented as a group IV insulated gate bipolar transistor (group IV IGBT). One or more of the III-Nitride transistor(s) may be situated over a body layer of the group IV IGBT, or the III-Nitride transistor(s) may be situated over a collector layer of the IGBT.

Abstract: According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.

Abstract: According to one disclosed embodiment, a semiconductor package for integrated passives and a semiconductor device comprises a high permeability structure formed over a surface of the semiconductor package and surrounding a contact body of the semiconductor package, the contact body being connected to an output of the semiconductor device. The contact body can be, for example, a solder bump. The high permeability structure causes a substantial increase in inductance of the contact body so as to form an increased inductance inductor coupled to the output of the semiconductor device. In one embodiment, the semiconductor package further comprises a blanket insulator formed over the high permeability structure, and a capacitor stack formed over the blanket insulator. In one embodiment, the semiconductor device comprises a group III-V power semiconductor device.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.