Abstract: An infrared charge transfer device (CTD) imaging system is disclosed which includes an optic system for focusing infrared energy emanating from a scene, a detector matrix for receiving the focused infrared energy and converting it to electrical signals representative of the intensity of the infrared energy, and a video processor for processing the electrical signals into video signals. The detector matrix of the system is a plurality of IR detector cells arranged in rows and columns. Each detector cell includes a substrate of semiconductor material, an integrating electrode, a drain electrode, a transfer electrode and insulating layers. The integrating electrode is centrally disposed with respect to the drain and transfer electrodes with the integrating electrode in a spaced relationship with the drain electrode. The integrating and drain electrodes form first level MIS electrodes on the semiconductor substrate.

Abstract: An infrared charge transfer device (CTD) imager system is disclosed which includes an optic system, a charge transfer device detector matrix and a signal processor. The optic system focuses infrared energy from a scene onto the detector matrix. The detector matrix produces electrical signals representative of the impinging energy and the signal processor processes the electrical signals into video signals. The CTD detector matrix comprises a plurality of charge injection devices (CID). Each CID has an IR sensitive area, and two metal/insulator/semiconductor gate electrodes surrounded by a field plate. One, a column gate electrode, is centrally located within the IR sensitive area and the other, a row gate electrode, surrounds the column gate electrode.

Abstract: A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.