Patents by Inventor Michael A. Kozuch

Michael A. Kozuch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7318141
    Abstract: Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventors: Steve M. Bennett, Gilbert Neiger, Erik C. Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Richard A. Uhlig, Larry Smith, Dion Rodgers, Andrew Glew, Erich Boleyn
  • Patent number: 7313669
    Abstract: In one embodiment, a method for supporting address translation in a virtual-machine environment includes creating a guest translation data structure to be used by a guest operating system for address translation operations, creating an active translation data structure based on the guest translation data structure, and periodically modifying the content of the active translation data structure to conform to the content of the guest translations data structure. The content of the active translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
  • Patent number: 7308576
    Abstract: An authenticated code module comprises a value that attests to the authenticity of the module. The value is encrypted with a key corresponding to a key of a computing device that is to execute the module.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: December 11, 2007
    Assignee: Intel Corporation
    Inventors: Andrew F. Glew, James A. Sutton, Lawrence O. Smith, David W. Grawrock, Gilbert Neiger, Michael A. Kozuch
  • Patent number: 7287197
    Abstract: In one embodiment, a request to transition control to a virtual machine (VM) is received from a virtual machine monitor (VMM) and a determination is made as to whether the VMM has requested a delivery of a fault to the VM. If the determination is positive, the fault is delivered to the VM when control is transitioned to the VM.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Michael Kozuch, Lawrence Smith, Scott Rodgers
  • Publication number: 20070234356
    Abstract: A method and system for support of personal computing in a public computing infrastructure. The system including a plurality of computers to be used by patrons of a public computing infrastructure. The system also includes one or more servers coupled to the plurality of computers via a network connection. Each of the plurality of computers includes a virtual machine monitor. The virtual machine monitor has a plurality of base virtual machine images, each of the base virtual machine images is customized for a particular hardware and software configuration representing a specific computing environment. The virtual machine monitor launches one of the plurality of base virtual machine images, arbitrates access to system resources via the launched virtual machine image, stores the changes in the state of the virtual machine image when a user terminates a session, and returns a computer to an appropriate state to enable the user to resume the terminated session in subsequent sessions.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Fernando Martins, Michael Kozuch
  • Patent number: 7272831
    Abstract: A method and apparatus for constructing host processor soft devices independent of the host processor operating system are provided. In one embodiment, a driver of a soft device is implemented in a virtual machine monitor (VMM), and the soft device is made available for use by one or more virtual machines coupled to the VMM. In an alternative embodiment, a software component of a soft device is implemented in a first virtual machine that is coupled to a VMM, and the soft device is made available for use by a second virtual machine coupled to the VMM.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Erik Cota-Robles, Stephen Chou, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Gilbert Neiger, Richard Uhlig
  • Publication number: 20070192577
    Abstract: An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.
    Type: Application
    Filed: January 24, 2006
    Publication date: August 16, 2007
    Inventors: Michael Kozuch, James Sutton, David Grawrock, Gilbert Neiger, Richard Uhlig, Bradley Burgess, David Poisner, Clifford Hall, Andy Glew, Lawrence Smith, Robert George
  • Patent number: 7225441
    Abstract: In one embodiment, a method for providing power management via virtualization includes monitoring the utilization of a host platform device by one or more virtual machines and managing power consumption of the host platform device based on the results of monitoring.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Michael Kozuch, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Sebastian Schoenberg, Richard Uhlig
  • Patent number: 7191440
    Abstract: Transitions among schedulable entities executing in a computer system are tracked in computer hardware or in a virtual machine monitor. In one aspect, the schedulable entities are operating system processes and threads, virtual machines, and instruction streams executing on the hardware. In another aspect, the schedulable entities are processes or threads executing within the virtual machines under the control of the virtual machine monitor. The virtual machine monitor derives scheduling information from the transitions to enable a virtual machine system to guarantee adequate scheduling quality of service to real-time applications executing in virtual machines that contain both real-time and non-real-time applications. In still another aspect, a parent virtual machine monitor in a recursive virtualization system can use the scheduling information to schedule a child virtual machine monitor that controls multiple virtual machines.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: March 13, 2007
    Assignee: Intel Corporation
    Inventors: Erik Cota-Robles, Sebastian Schoenberg, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Gilbert Neiger, Richard Uhlig
  • Patent number: 7127548
    Abstract: In one embodiment, a command pertaining to one or more portions of a register is received from guest software. Further, a determination is made as to whether the guest software has access to all of the requested portions of the register based on indicators within a mask field that correspond to the requested portions of the register. If the guest software has access to all of the requested portions of the register, the command received from the guest software is executed on the requested portions of the register.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Steve Bennett, Andrew V. Anderson, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Michael A. Kozuch
  • Patent number: 7124273
    Abstract: A method and an apparatus are used to efficiently translate memory addresses. The translation scheme yields a translated address, a memory type for the translated address, and a fault bit for the translation.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Andy Glew, Michael A. Kozuch, Erich S. Boleyn, Lawrence O. Smith, III, Gilbert Neiger, Richard Uhlig
  • Patent number: 7124327
    Abstract: In one embodiment, fault information relating to a fault associated with the operation of guest software is received. Further, a determination is made as to whether the fault information satisfies one or more filtering criterion. If the determination is positive, control remains with the guest software and is not transferred to the virtual machine monitor (VMM).
    Type: Grant
    Filed: June 29, 2002
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Steve Bennett, Andrew V. Anderson, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Xiang Zou, Michael A. Kozuch
  • Publication number: 20060155967
    Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.
    Type: Application
    Filed: January 13, 2006
    Publication date: July 13, 2006
    Inventors: Hong Wang, Ralph Kling, Yong-Fong Lee, David Berson, Michael Kozuch, Konrad Lai
  • Patent number: 7073042
    Abstract: In one embodiment, when it is determined that a modification of content of an active address translation data structure is required, an entry in the active address translation data structure is modified to conform to a corresponding entry in a guest address translation data structure. During the modification, a bit field including one or more access control indicators in the entry of the active address translation data structure is not overwritten with corresponding data from the guest address translation data structure.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Richard Uhlig, Gilbert Neiger, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Steven M Bennett
  • Patent number: 7035963
    Abstract: In one embodiment, a method for resolving address space conflicts includes detecting that a guest operating system attempts to access a region occupied by a first portion of a virtual machine monitor and relocating the first portion of the virtual machine monitor within the first address space to allow the guest operating system to access the region previously occupied by the first portion of the virtual machine monitor.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
  • Publication number: 20060075402
    Abstract: In one embodiment, a method includes transitioning control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a VMM timer indicator is set to an enabling value, and identifying a VMM timer value configured by the VMM. The method further includes periodically comparing a current value of a timing source with the VMM timer value, generating an internal event if the current value of the timing source has reached the VMM timer value, and transitioning control to the VMM in response to the internal event without incurring an event handling procedure in any one of the VMM and the VM.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Gilbert Neiger, Steven Bennett, Erik Cota-Robles, Sebastian Schoenberg, Clifford Hall, Dion Rodgers, Lawrence Smith, Andrew Anderson, Richard Uhlig, Michael Kozuch, Andy Glew
  • Patent number: 7024555
    Abstract: An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value in order to establish security verification of secure software within the secure memory environment.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: Michael A. Kozuch, James A. Sutton, II, David Grawrock, Gilbert Neiger, Richard A. Uhlig, Bradley G. Burgess, David I. Poisner, Clifford D. Hall, Andy Glew, Lawrence O. Smith, III, Robert George
  • Patent number: 7020738
    Abstract: One embodiment of the invention is method for resolving address space conflicts between a virtual machine monitor and a guest operating system. The method includes allocating an address space for the operating system and an address space for the monitor. The method also includes mapping a portion of the monitor into the address space allocated for the operating system and the address space allocated for the monitor, and locating another portion of the monitor in the address space allocated for the monitor. The method also includes detecting that the operating system attempts to access a region occupied by the portion of the monitor within the address space allocated for the operating system, and relocating that portion of the monitor within that address space to allow the operating system to access the region previously occupied by that portion of the monitor.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jevasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
  • Patent number: 7020766
    Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Hong Wang, Ralph Kling, Yong-Fong Lee, David A. Berson, Michael A. Kozuch, Konrad Lai
  • Publication number: 20050240751
    Abstract: In one embodiment, a method for supporting address translation in a virtual-machine environment includes creating a guest translation data structure to be used by a guest operating system for address translation operations, creating an active translation data structure based on the guest translation data structure, and periodically modifying the content of the active translation data structure to conform to the content of the guest translations data structure. The content of the active translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).
    Type: Application
    Filed: February 28, 2005
    Publication date: October 27, 2005
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg