Abstract: Embodiments of the present invention generally provide m Methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

Abstract: One embodiment of the present invention sets forth a system for computing and error checking configuration parameters related to raster image generation within a graphics processing unit. Input parameters are validated by a hardware-based error checking engine. A hardware-based pre-calculation engine uses validated input parameters to compute additional private configuration parameters used by the raster image generation circuitry within a graphics processing unit.

Abstract: An isochronous processor includes a state register, a functional unit, a control module, and an activation unit. The state register includes an arm buffer and an active buffer. The functional unit performs a transformation operation on the data stream in response to an active value of the control parameter obtained from the active buffer. The control module updates the arm value of the control parameter in the arm buffer in response to control instructions. The activation unit detects a load event propagating with the data stream and transfers the parameter value from the arm buffer to the active buffer in response to the load event. During this transfer, the control module is inhibited from updating the arm buffer.

Abstract: Embodiments of the present invention generally provide m Methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

Abstract: A system and method for enabling or disabling clocks to one or more portions of hardware circuitry, for example a display sub-system of a personal computer. A processor generates a command or data to a first circuit configured to perform a function based at least on the command or data. A clock generator selectively supplies clocks to the first circuit and a second circuit configured to perform a second function. A software interface circuit coupled to the processor and the clock generator autonomously determines based at least on the command or data whether the second circuit will perform the second function or be idle in an upcoming period and disables one or more of the clocks to the second circuit if the second circuit will be idle in the upcoming period.

Abstract: In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.

Abstract: An output pipeline for a video processing device provides supersampling of the output data the digital domain to eliminate or reduce unwanted frequency components in an analog output signal. An encoder converts a pixel stream to digital sample values for a target analog signal at a base sampling rate. The base data stream is supersampled, and the supersampled data is provided to a digital to analog converter The supersampling rate can be selected so as to provide substantial attenuation of a higher frequency echo in the analog output signal.

Abstract: A display refresh system, method and computer program product are provided. In use, a refresh rate is adjusted for power saving purposes, and/or any other purpose(s) for that matter. Further, various embodiments are provided for reducing visual manifestations associated with a transition between a first refresh rate and a second refresh rate.

Abstract: A system and method for enabling or disabling clocks to one or more portions of hardware circuitry, for example a display sub-system of a personal computer. A processor generates a command or data to a first circuit configured to perform a function based at least on the command or data. A clock generator selectively supplies clocks to the first circuit and a second circuit configured to perform a second function. A software interface circuit coupled to the processor and the clock generator autonomously determines based at least on the command or data whether the second circuit will perform the second function or be idle in an upcoming period and disables one or more of the clocks to the second circuit if the second circuit will be idle in the upcoming period.

Abstract: A system and method for managing access to a shared resource employs mutually exclusive flags. The flags enable arbitration between all applications requesting the use of the shared resource and ensure that each application has exclusive and continuous use of the shared resource. The preferred embodiment uses hardware to realize the flags and the flag arbitrating means. In one embodiment, the applications control and observe the flags through read/write registers. Alternative embodiments provide a unique read/write register for each application using the shared resource.

Abstract: Embodiments of the present invention generally provide m Methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

Abstract: In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.

Abstract: An output pipeline for a video processing device provides supersampling of the output data the digital domain to eliminate or reduce unwanted frequency components in an analog output signal. An encoder converts a pixel stream to digital sample values for a target analog signal at a base sampling rate. The base data stream is supersampled, and the supersampled data is provided to a digital to analog converter The supersampling rate can be selected so as to provide substantial attenuation of a higher frequency echo in the analog output signal.

Abstract: Embodiments of the present invention generally provide m Methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

Abstract: A disk-assisted system for editing video tapes. Source material from video tapes is logged onto random access storage such as a hard disk drive using of a Macintosh-based computer system. At any one time, only a small portion of the tape material is stored as video frames on the computer disk. By software control, material is cached back and forth between the computer disk and the video tape. Thus editing is accomplished and an edit decision list constructed for compilation of the final video production. This provides the advantage of fast access time for editing of the material which is on the disk while allowing actual physical editing at the end of the project of the actual video tape material. The processes of logging the material onto the disk and editing the final tape are performed automatically.

Abstract: A control system is coupled to control a system for spatially transforming images by separate transformation of each dimension of the image. The control system includes a control panel having a three-axis joystick and a set of keys providing function selection and assignment of the joystick to a particular control function, a panel processor coupled to receive and interpret control panel data and a high level controller. The high level controller responds to the operator control information from the panel processor to establish selected image transformation information at selected knot points and communicates to a transformation portion of the transformation system data controlling the transformation of each image field with data for fields between knot points being developed from a cubic spline interpolation between knot points.