Abstract: A successive approximation analog-to-digital converter (SA-ADC) includes a reference generator configured to output a first voltage and a second voltage; a comparator, the comparator having a positive input and a negative input thereto, the comparator being configured to receive the first voltage and the second voltage; and a comparator input toggle located between the reference generator and the comparator, wherein the comparator input toggle is configured to receive the first and second voltages from the reference generator and provide the first and second voltages to the comparator, wherein the comparator input toggle is further configured to switch between a first position, in which the first voltage is connected to the positive input, and the second voltage is connected to the negative input, and a second position, in which the second voltage is connected to the positive input, and the first voltage is connected to the negative input.

Abstract: A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.

Abstract: An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated cir

Abstract: Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage.

Abstract: A voltage regulator includes a regulator input connected to a reference voltage; a regulator output that outputs a regulated voltage to an electrical load; a first loop, the first loop configured to receive the reference voltage, the first loop outputting a bias voltage; a second loop, the second loop configured to receive the bias voltage as an input; and a bias voltage capacitor connected to a node between the first loop and the second loop.

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.

Abstract: The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.

Abstract: A method and apparatus for generating a voltage that is proportional to an absolute temperature (PTAT voltage). A current generator for generating a current that is proportional to absolute temperature (PTAT current) has an internal resistance and two diodes. The PTAT current is proportional to the resistance, and the temperature coefficient of the PTAT current is defined by the ratio of diode current densities. A feedback circuit has a source follower that is connected to the current generator for driving the output node with a regulated PTAT current wherein the PTAT current is mirrored accurately, providing a constant Vref.

Abstract: On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.

Abstract: A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected to the transistor drain. The system may further include an additional transistor and an additional transistor gate carried by the additional transistor and connected to the transistor gate. The system may additionally include an additional transistor drain to receive the reference current mirrored from the additional transistor.

Abstract: A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated cir

Abstract: On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.

Abstract: A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected to the transistor drain. The system may further include an additional transistor and an additional transistor gate carried by the additional transistor and connected to the transistor gate. The system may additionally include an additional transistor drain to receive the reference current mirrored from the additional transistor.

Abstract: A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage.

Abstract: A system to generate a reference for a charge pump may include a diode-connected transistor providing a reference voltage, and an output transistor. The system may also include a reference circuit to provide a current that is substantially temperature insensitive and the reference circuit delivers the current across the diode-connected transistor thereby enabling the reference voltage to move with processing of the diode-connected transistor.

Abstract: A system to improve a voltage multiplier may include a voltage multiplier circuit, and a capacitor carried by the multiplier circuit. The system may also include a transistor to charge an up voltage of the capacitor.

Abstract: A system to evaluate charge pump output may include a comparator to compare a charge pump output voltage to a reference voltage to generate a comparison result. The system may also include a divider to divide down a clock signal. The system may further include a logical conjunction unit to operate on the comparison result and the divided down clock signal.