Abstract: A satellite positioning receiver. The receiver comprises: an RF front end, for receiving satellite positioning signals; an analog to digital converter, for sampling the received signals to generate signal samples; a memory; and a processor, for processing the signal samples to derive code-phases and pseudo-ranges and to calculate a position fix. The processor has a first mode in which it is operable to process the samples as they are generated, to calculate the position fix. It also has a second mode in which it is operable to store the samples or the code-phases or pseudo-ranges in the memory for later processing.

Abstract: An acquisition unit of a GNSS receiver base band circuit includes an integrator with a number of preprocessors where an incoming digital signal is mixed with different frequency signals to compensate at least in part for clock drift and Doppler shifts. The resulting digital signals are, after an accumulation step reducing sample frequency, integrated over an integration period extending over several basic intervals of the length of a basic sequence characteristic for a GNSS satellite, so that samples separated by a multiple of the basic interval are superposed. The resulting data sequence of 1,023 digital values is stored in one of two memories and then, in mixers, sequentially shifted by post-integration frequencies which are multiples of the inverse of the length of the basic interval. The pre-integration frequencies employed in the preprocessors deviate, with one possible exception, from the post-integration frequencies and are usually smaller.

Abstract: In a GNSS receiver data sequences derived from a digital signal each with an internally generated correlation sequence derived from a basic sequence and mixed with frequency signals corresponding to various Doppler frequencies and in various phase positions with respect to the data sequence are correlated and the correlation values evaluated. In difficult conditions, e.g., RF levels of the signal of ?145 dBm and less, correlation values produced with the same correlation sequence and phase position but with a plurality of data sequences are evaluated together in that, in an evaluator (49), every-correlation value is, in a comparator (52), compared with at least a first value threshold and a second value threshold, with the latter having a value between 1.3 and 1.7 times the value of the first and values ?1, 0 or +1 assigned accordingly to a correlation term which is then added to an integer correlation counter which varies over a counter interval, e.g., [0, 15], in an adding unit (53).

Abstract: An acquisition unit of a GNSS receiver base band circuit includes an integrator with a number of preprocessors where an incoming digital signal is mixed with different frequency signals to compensate at least in part for clock drift and Doppler shifts. The resulting digital signals are, after an accumulation step reducing sample frequency, integrated over an integration period extending over several basic intervals of the length of a basic sequence characteristic for a GNSS satellite, so that samples separated by a multiple of the basic interval are superposed. The resulting data sequence of 1,023 digital values is stored in one of two memories and then, in mixers, sequentially shifted by post-integration frequencies which are multiples of the inverse of the length of the basic interval. The pre-integration frequencies employed in the preprocessors deviate, with one possible exception, from the post-integration frequencies and are usually smaller.

Abstract: A satellite positioning receiver. The receiver comprises: an RF front end, for receiving satellite positioning signals; an analogue to digital converter, for sampling the received signals to generate signal samples; a memory; and a processor, for processing the signal samples to derive code-phases and pseudo-ranges and to calculate a position fix. The processor has a first mode in which it is operable to process the samples as they are generated, to calculate the position fix. It also has a second mode in which it is operable to store the samples or the code-phases or pseudo-ranges in the memory for later processing.

Abstract: An acquisition unit of a GNSS receiver base band circuit includes an integrator with a number of preprocessors where an incoming digital signal is mixed with different frequency signals to compensate at least in part for clock drift and Doppler shifts. The resulting digital signals are, after an accumulation step reducing sample frequency, integrated over an integration period extending over several basic intervals of the length of a basic sequence characteristic for a GNSS satellite, so that samples separated by a multiple of the basic interval are superposed. The resulting data sequence of 1,023 digital values is stored in one of two memories and then, in mixers, sequentially shifted by post-integration frequencies which are multiples of the inverse of the length of the basic interval, The pre-integration frequencies employed in the preprocessors deviate, with one possible exception, from the post-integration frequencies and are usually smaller.

Abstract: In a GNSS receiver data sequences derived from a digital signal each with an internally generated correlation sequence derived from a basic sequence and mixed with frequency signals corresponding to various Doppler frequencies and in various phase positions with respect to the data sequence are correlated and the correlation values evaluated. In difficult conditions, e.g., RF levels of the signal of ?145 dBm and less, correlation values produced with the same correlation sequence and phase position but with a plurality of data sequences are evaluated together in that, in an evaluator (49), every-correlation value is, in a comparator (52), compared with at least a first value threshold and a second value threshold, with the latter having a value between 1.3 and 1.7 times the value of the first and values ?1, 0 or +1 assigned accordingly to a correlation term which is then added to an integer correlation counter which varies over a counter interval, e.g., [0, 15], in an adding unit (53).

Abstract: An acquisition unit of a GNSS receiver base band circuit comprises an integrator (27) with a number of preprocessors (29a-h) where an incoming digital signal is mixed with different frequency signals to compensate at least in part for clock drift and Doppler shifts. The resulting digital signals are in each case, after an accumulation step reducing sample frequency, integrated over an integration period extendinging over several, e.g., twenty, basic intervals of the length of a basic sequence characteristic for a GNSS satellite, usually 1 ms, in such a way that samples separated by a multiple of the basic interval are superposed.

Abstract: A multi-processor computer system is described that consists of at least two processors equipped with storage means. Each of the processors is assigned at least one private storage area (10) in the storage means. Furthermore, at least one common storage area (16) is provided in the storage means, to which a portion (13) of the private storage area (10) is assigned. Through this storage means arrangement, it is possible, using appropriate commands, to transfer messages between different processors via common storage areas. The management of the private and common storage areas is accomplished using tables, whereby the use of help tables simplifies locating information required for carrying out specific commands.