Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.

Abstract: A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N×analog values corresponding to N×levels of its drain current (ID) or threshold voltage (VT) levels, representing N×weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.

Abstract: A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N×analog values corresponding to N×levels of its drain current (ID) or threshold voltage (VT) levels, representing N×weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.

Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.

Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.

Abstract: The present invention provides a method and a computer-readable program for providing generation of graphical congestion images during placement driven synthesis optimization. These graphical congestion images enable a design engineer to make changes and/or improvements to subsequent processes in the design flow before the current placement driven synthesis step completes, thus saving time. This information also provides valuable debug information to PDS developers.