Abstract: The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface.

Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.

Abstract: Examples of the present disclosure relate to an apparatus comprising interface circuitry to receive memory access commands directed to a memory device, each memory access command specifying a memory address to be accessed. The apparatus comprises scheduler circuitry to store a representation of a plurality of states accessible to the memory device and, based on the representation, determine an order for the received memory access commands. The apparatus comprises dispatch circuitry to receive the received memory access commands from the scheduler circuitry and issue the received memory access commands, in the determined order, to be performed by the memory device.

Abstract: The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.

Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.

Abstract: Apparatuses and method are disclosed for protecting the integrity of data stored in a protected area of memory. Data in the protected area of memory is retrieved in data blocks and an authentication code is associated with a memory granule contiguously comprising a first data block and a second data block. Calculation of the authentication code comprises a cryptographic calculation based on a first hash value determined from the first data block and a second hash value determined from the second data block. A hash value cache is provided to store hash values determined from data blocks retrieved from the protected area of the memory. When the first data block and its associated authentication code are retrieved from memory, a lookup for the second hash value in the hash value cache is performed, and a verification authentication code is calculated for the memory granule to which that data block belongs.

Abstract: The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

Abstract: There is provided an apparatus comprising scheduling circuitry, which selects a task as a selected task to be performed from a plurality of queued tasks, each having an associated priority, in dependence on the associated priority of each queued task. Escalating circuitry increases the associated priority of each of the plurality of queued tasks after a period of time. The plurality of queued tasks comprises a time-sensitive task having an associated deadline and in response to the associated deadline being reached, the scheduling circuitry selects the time-sensitive task as the selected task to be performed.

Abstract: The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device.

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device.

Abstract: A cache to provide data caching in response to data access requests from at least one system device, and a method operating such a cache, are provided. Allocation control circuitry of the cache is responsive to a cache miss to allocate an entry of the multiple entries in the data caching storage circuitry in dependence on a cache allocation policy. Quality-of-service monitoring circuitry is responsive to a quality-of-service indication to modify the cache allocation policy with respect to allocation of the entry for the requested data item. The behaviour of the cache, in particular regarding allocation and eviction, can therefore be modified in order to seek to maintain a desired quality-of-service for the system in which the cache is found.

Abstract: A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements provided within the storage device. Memory access execution circuitry is used to issue to a physical layer interface access requests selected from the storage device, for onward propagation from the physical layer interface to the memory device. Control circuitry is responsive to a training event to initiate a training operation of the physical layer interface. In addition, the control circuitry is further responsive to the training event to trigger performance of the maintenance operation by the maintenance circuitry whilst the training operation is being performed.

Abstract: A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.

Abstract: An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller orchestrates direct data transfer by issuing a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than via the memory controller. One of the first and second memory modules may be used as a cache for data stored in the other memory module. The direct data transfer may comprise a data move or a data copy operation.

Abstract: A cache to provide data caching in response to data access requests from at least one system device, and a method operating such a cache, are provided. Allocation control circuitry of the cache is responsive to a cache miss to allocate an entry of the multiple entries in the data caching storage circuitry in dependence on a cache allocation policy. Quality-of-service monitoring circuitry is responsive to a quality-of-service indication to modify the cache allocation policy with respect to allocation of the entry for the requested data item. The behaviour of the cache, in particular regarding allocation and eviction, can therefore be modified in order to seek to maintain a desired quality-of-service for the system in which the cache is found.

Abstract: The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.

Abstract: An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller is arranged to orchestrate direct data transfer by transmitting a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than requiring the data to have been routed via the memory controller, and then stores that data in dependence on the second direct transfer command. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.