Abstract: A topical nerve activation patch includes a flexible substrate, a dermis conforming bottom surface of the substrate comprising adhesive and adapted to contact a dermis of a user, a flexible top outer surface of the substrate approximately parallel to the bottom surface, a plurality of electrodes positioned on the patch proximal to the bottom surface and located beneath the top outer surface and coupled to the flexible substrate, a power source, and electronic circuitry that generates an output voltage applied to the electrodes. The electronic circuitry includes a controller, a voltage monitoring circuit coupled to the controller, a current monitoring circuit coupled to the controller, a switch coupled to the controller and a boosted voltage circuit coupled to the switch and the power source.

Abstract: A topical nerve activation patch includes a flexible substrate, a dermis conforming bottom surface of the substrate comprising adhesive and adapted to contact a dermis of a user, a flexible top outer surface of the substrate approximately parallel to the bottom surface, a plurality of electrodes positioned on the patch proximal to the bottom surface and located beneath the top outer surface and coupled to the flexible substrate, a power source, and electronic circuitry that generates an output voltage applied to the electrodes. The electronic circuitry includes a controller, a voltage monitoring circuit coupled to the controller, a current monitoring circuit coupled to the controller, a switch coupled to the controller and a boosted voltage circuit coupled to the switch and the power source.

Abstract: A data packet is provided that includes a synchronization field and an acknowledgement field indicative of an acknowledgement of receipt of a prior data packet. The data packet also includes a response field that includes information indicative of a system fault, a header field, and a sequence number field that includes a number assigned to the data packet. The data packet further includes a data field, an end of packet field, and an error-checking field. Methods and computer program products are provided that, in some implementations, include retransmitting packets if the acknowledgement field in a received data packet is a no acknowledgement (NAK) and/or placing a node into a safe state in response to a fault signal that is included in the received data packet.

Abstract: A data packet is provided that includes a synchronization field and an acknowledgement field indicative of an acknowledgement of receipt of a prior data packet. The data packet also includes a response field that includes information indicative of a system fault, a header field, and a sequence number field that includes a number assigned to the data packet. The data packet further includes a data field, an end of packet field, and an error-checking field. Methods and computer program products are provided that, in some implementations, include retransmitting packets if the acknowledgement field in a received data packet is a no acknowledgement (NAK) and/or placing a node into a safe state in response to a fault signal that is included in the received data packet.

Abstract: A data packet is provided that includes a synchronization field and an acknowledgement field indicative of an acknowledgement of receipt of a prior data packet. The data packet also includes a response field that includes information indicative of a system fault, a header field, and a sequence number field that includes a number assigned to the data packet. The data packet further includes a data field, an end of packet field, and an error-checking field. Methods and computer program products are provided that, in some implementations, include retransmitting packets if the acknowledgement field in a received data packet is a no acknowledgement (NAK) and/or placing a node into a safe state in response to a fault signal that is included in the received data packet.

Abstract: Methods, apparatus, and computer program products that synchronously communicate data packets between a first node and a second node. Data packets are transmitted from the first node without waiting for acknowledgment of receipt by the second node. Acknowledgment of receipt of a given data packet is subsequently received at the first node. The acknowledgement is received substantially at a predetermined time following transmission of the given data packet. The acknowledgement indicates that the second node received the given data packet uncorrupted.

Abstract: Methods, systems, and computer program products for transmitting first-priority data and second-priority data. The first-priority data and second-priority data are stored in separate data buffers, and the first-priority data is transmitted preferentially over the second-priority data.

Abstract: Methods, systems, and computer program products for transmitting first-priority data and second-priority data. The first-priority data and second-priority data are stored in separate data buffers, and the first-priority data is transmitted preferentially over the second-priority data.

Abstract: A memory system for use in a computer which in the preferred embodiment provides two megabytes of capacity per board (up to four boards) is disclosed. An ALU generates an address signal which selects a number of set locations in the main memory. Simultaneously, a portion of the address field is fed to a set association logic circuit for parallel processing. The set association circuit contains tag storage memories and comparators which store tag values. These values are compared with address fields, and if a match occurs, one of the comparators selects a 128-bit word from the main memory. A hash function is also used to provide for dispersal of storage locations to reduce the number of collisions of frequently used addresses. Because of hardware implementation of hashing and least recently used (LRU) algorithm, a constant predetermined cycle time is realized since all accessing functions occur substantially in parallel.

Abstract: A digital data system having a memory with a unique multi-ported memory I/O means. Separate means are provided for communicating with any of several buses. Address information, operands, instructions and Input/Output data may be separately sent and received over various of the buses.

Abstract: A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege.

Abstract: A unique frequency synthesizer unit for use in a data processing system I/O interface unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics.

Abstract: A data processing system the central processing unit (CPU) of which is responsive to and executes microinstructions generated by the decoding of macroinstructions so as to provide one or more data processing operations. The system is arranged so that such microinstructions can be supplied to the CPU from a CPU-resident microcode decoding logic or from one or more external microcode decoding units. Each of the external units can identify a macroinstruction which it is capable of decoding and includes logic for externally providing one or more microinstructions which result from the decoding process. If an external microcode unit and the CPU-resident decode logic are both capable of such decoding operation, the external unit overrides the CPU decoding logic and controls the decoding operation externally. The external microcode unit includes logic for monitoring the number of microinstructions supplied to the CPU which have not yet been executed by the CPU.

Abstract: A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second or "vertical", microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more "modifier" fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations.

Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege.

Abstract: A data processing system in which the bits of each stored word in a memory thereof are refreshed periodically. At substantially the same time the refresh operation with respect to each word occurs, an error detection operation also occurs and, if an error is detected in a word that is being refreshed, the error is then corrected and the corrected word is written back into the memory. Thus, errors are continuously being checked with no more use of machine time then is required for the refresh operation. Error correction, when necessary, then takes place at a fixed frequency, a limit thereby being placed on the error correction process. If errors in a work are detected when the word is requested for access by a requestor, the error is corrected before the word is supplied to the requestor but the corrected word is not written back into memory at that time, the word in memory being again detected and corrected at its next refresh operation.

Abstract: A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second, or "vertical", microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more "modifier" fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations. Unique bus protocol signals are generated to prevent simultaneous access to the system bus by two competing system components and to permit substantially immediate control of the systems bus by a component without requiring a CPU decision thereon.

Abstract: A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage.

Abstract: A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage.

Abstract: A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage.