Abstract: Embodiments of the invention include method, systems and computer program products for servicing indirect storage requests. Method includes decoding a storage request instruction and sending to a first one of a plurality of memory controllers an address represented by a first pointer associated with at least a portion of the storage request instruction. A first memory is used to read information associated with a second pointer contained at the address. The first memory forwards the storage request instruction to a second one of the plurality of memory controllers, wherein the second one of the plurality of memory controllers is associated with and/or manages a memory location represented by the second pointer. The second one of the plurality of memory controllers reads and forwards data associated with the storage request instruction to a processor using the second pointer. The processor writes the forwarded data in a destination register of the processor.

Abstract: Systems, methods and computer program products using multi-tag storage to enable efficient data compression in caches without increasing a tag/data area overhead. One method can comprise storing compressed versions of data elements in a data array of a cache, with tags for the compressed versions respectively appended to the compressed versions as stored in the data array, and storing hashed versions of the tags in a tag array of the cache, wherein the hashed versions of the tags respectively have fewer bits than the tags. A tag block may store hashed versions of tags corresponding to first and second compressed data elements stored in a cacheline of the cache. Hashed tag entries may be compared with full versions of the tags appended to compressed versions of data elements stored in the data array to prevent false positive cache reads. A compressed identifier (CID) may be stored with the hashed versions of tags in the tag array.

Abstract: Embodiments include method, systems and computer program products for fusing one or more transaction request messages. The computer-implemented method includes comparing, using a memory controller, at least two electronic transaction request messages and determining if the at least two electronic transaction request messages are of a same electronic transaction request message type. The memory controller is used to determine that the at least two electronic transaction request messages are directed to associated portions of memory based at least in part on determining that the at least two electronic transaction request messages are the same electronic transaction request message type. The memory controller fuses the at least two electronic transaction request messages based at least in part on determining that the at least two electronic transaction request messages are directed to associated portions of memory.

Abstract: A computer-implemented method includes receiving, at a memory controller, a new transaction request referencing a new transaction to be executed on a memory. The memory includes two or more memory groups embodying two or more memory technologies, and the memory controller includes two or more group request queues with a respective group request queue corresponding to each memory group of the two or more memory groups. A memory group is selected, by the memory controller, from among the two or more memory groups. The transaction request is placed, by the memory controller, on the respective group request queue corresponding to the selected memory group. The new transaction is executed on the selected memory group. A new response to the new transaction is received, by the memory controller, from the selected memory group. The new response is returned.

Abstract: Systems, methods and computer program products using multi-tag storage to enable efficient data compression in caches without increasing a tag/data area overhead. One method can comprise storing compressed versions of data elements in a data array of a cache, with tags for the compressed versions respectively appended to the compressed versions as stored in the data array, and storing hashed versions of the tags in a tag array of the cache, wherein the hashed versions of the tags respectively have fewer bits than the tags. A tag block may store hashed versions of tags corresponding to first and second compressed data elements stored in a cacheline of the cache. Hashed tag entries may be compared with full versions of the tags appended to compressed versions of data elements stored in the data array to prevent false positive cache reads. A compressed identifier (CID) may be stored with the hashed versions of tags in the tag array.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: A computer-implemented method includes receiving, at a memory controller, a new transaction request referencing a new transaction to be executed on a memory. The memory includes two or more memory groups embodying two or more memory technologies, and the memory controller includes two or more group request queues with a respective group request queue corresponding to each memory group of the two or more memory groups. A memory group is selected, by the memory controller, from among the two or more memory groups. The transaction request is placed, by the memory controller, on the respective group request queue corresponding to the selected memory group. The new transaction is executed on the selected memory group. A new response to the new transaction is received, by the memory controller, from the selected memory group. The new response is returned.

Abstract: Embodiments include method, systems and computer program products for fusing one or more transaction request messages. The computer-implemented method includes comparing, using a memory controller, at least two electronic transaction request messages and determining if the at least two electronic transaction request messages are of a same electronic transaction request message type. The memory controller is used to determine that the at least two electronic transaction request messages are directed to associated portions of memory based at least in part on determining that the at least two electronic transaction request messages are the same electronic transaction request message type. The memory controller fuses the at least two electronic transaction request messages based at least in part on determining that the at least two electronic transaction request messages are directed to associated portions of memory.

Abstract: Embodiments of the invention include method, systems and computer program products for servicing indirect storage requests. Method includes decoding a storage request instruction and sending to a first one of a plurality of memory controllers an address represented by a first pointer associated with at least a portion of the storage request instruction. A first memory is used to read information associated with a second pointer contained at the address. The first memory forwards the storage request instruction to a second one of the plurality of memory controllers, wherein the second one of the plurality of memory controllers is associated with and/or manages a memory location represented by the second pointer. The second one of the plurality of memory controllers reads and forwards data associated with the storage request instruction to a processor using the second pointer. The processor writes the forwarded data in a destination register of the processor.

Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.