Patents by Inventor Michael B. Mitchell
Michael B. Mitchell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11372757Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.Type: GrantFiled: September 4, 2020Date of Patent: June 28, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Kevin Neal Magill, Eric Francis Robinson, Derek Bachand, Jason Panavich, Michael B. Mitchell, Michael P. Wilson
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Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices
Patent number: 11354239Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.Type: GrantFiled: September 18, 2020Date of Patent: June 7, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Eric Francis Robinson, Kevin Neal Magill, Jason Panavich, Derek Bachand, Michael B. Mitchell, Michael P. Wilson -
MAINTAINING DOMAIN COHERENCE STATES INCLUDING DOMAIN STATE NO-OWNED (DSN) IN PROCESSOR-BASED DEVICES
Publication number: 20220091979Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Eric Francis ROBINSON, Kevin Neal MAGILL, Jason PANAVICH, Derek BACHAND, Michael B. MITCHELL, Michael P. WILSON -
Publication number: 20220075726Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Kevin Neal MAGILL, Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Michael B. MITCHELL, Michael P. WILSON
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Patent number: 11138114Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.Type: GrantFiled: January 8, 2020Date of Patent: October 5, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Kevin Neal Magill, Eric Francis Robinson, Derek Bachand, Jason Panavich, Michael P. Wilson, Michael B. Mitchell
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Patent number: 11093396Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.Type: GrantFiled: November 8, 2019Date of Patent: August 17, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Eric Francis Robinson, Derek Bachand, Jason Panavich, Kevin Neal Magill, Michael B. Mitchell, Michael P. Wilson
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Publication number: 20210209026Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventors: Kevin Neal MAGILL, Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Michael P. WILSON, Michael B. MITCHELL
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Publication number: 20210141726Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.Type: ApplicationFiled: November 8, 2019Publication date: May 13, 2021Inventors: Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Kevin Neal MAGILL, Michael B. MITCHELL, Michael P. WILSON
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Patent number: 8301992Abstract: A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.Type: GrantFiled: August 7, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Anthony J. Bybell, Michael B. Mitchell, Jason M. Sullivan
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Publication number: 20110035643Abstract: A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.Type: ApplicationFiled: August 7, 2009Publication date: February 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Bybell, Michael B. Mitchell, Jason M. Sullivan
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Patent number: 7672188Abstract: A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.Type: GrantFiled: December 12, 2007Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Matthew W. Baker, Benjamin J. Bowers, Michael B. Mitchell, Nishith Rohatgi
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Publication number: 20090154283Abstract: A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.Type: ApplicationFiled: December 12, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Correale, JR., Matthew W. Baker, Benjamin J. Bowers, Michael B. Mitchell, Nishith Rohatgi
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Patent number: 7319578Abstract: A method and apparatus are provided for determining power events on an I/C chip for undissipated power to the chip, and wherein the chip includes a plurality of separately regulatable power consumers. A structure is provided for monitoring the occurrence of each power event to each power consumer, and determining the dissipation of power from each power event, and controlling power used by the chip responsive to the amount of undissipated power.Type: GrantFiled: June 8, 2005Date of Patent: January 15, 2008Assignee: International Business Machines CorporationInventors: James N. Dieffenderfer, Praveen Karandikar, Michael B. Mitchell, Thomas P. Speier, Paul M. Steinmetz
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Patent number: 6623760Abstract: Methods of preparing particulates for agglomeration, having a specified particle size distribution and desired convertible amorphous content, are described. The method involves a plurality of micronizing steps at least two of which are separated by a curing step. In the curing step, a stimulus such as humidity may be used to crystallize at least some, and in many instances preferably all, of the convertible amorphous content.Type: GrantFiled: January 26, 2000Date of Patent: September 23, 2003Assignee: Schering CorporationInventors: Tsong-Toh Yang, Stephen K. C. Yu, Charles G. Eckhart, Michael B. Mitchell
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Patent number: 6506767Abstract: Crystalline polymorphs of 8-chloro-6,11-dihydro-11-(4-piperidylidene)-5H-benzo[5,6]cycloheptic[1,2-b]pyridine represented by the formula pharmaceutical compositions containing such polymorphs, and methods of using such polymorphs to treat allergic reactions in mammals such as man are disclosed.Type: GrantFiled: July 1, 1998Date of Patent: January 14, 2003Assignee: Schering CorporationInventors: Doris P. Schumacher, Junning Lee, Lawrence R. Rogers, Charles G. Eckhart, Naneshwar S. Sawant, Michael B. Mitchell
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Patent number: 4782159Abstract: A process for the prepartion of 3-[4-(4-oxo-1,4-dihydropyridin-1-yl)benzoyl]butanoic acid which comprises the reaction of 3-(4-fluorobenzoyl)butanoic acid with 4-hydroxypyridine under aqueous conditions in the presence of a base.Type: GrantFiled: January 29, 1988Date of Patent: November 1, 1988Assignee: Smith Kline & French Laboratories LimitedInventors: Michael B. Mitchell, Kiritkant D. Pancholi