Abstract: An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop may be provided to allow the user to adjust the sensitivity of the system to earthquakes. A mesh net that rolls down may be provided to provide additional security to items being stored on the shelf.

Abstract: An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop may be provided to allow the user to adjust the sensitivity of the system to earthquakes. A mesh net that rolls down may be provided to provide additional security to items being stored on the shelf.

Abstract: An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop is located along a back portion of the retainer rest portion. The position of the rest stop can be adjusted to adjust the sensitivity of the system to earthquakes. The guide rails have retainer stops located at selected positions to keep the retainer from moving past. In one embodiment two retainers are provided and in another embodiment, a mesh is provided to contain items that would otherwise fall through.

Abstract: An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop is located along a back portion of the retainer rest portion. The position of the rest stop can be adjusted to adjust the sensitivity of the system to earthquakes. The guide rails have retainer stops located at selected positions to keep the retainer from moving past. In one embodiment two retainers are provided and in another embodiment, a mesh is provided to contain items that would otherwise fall through.

Abstract: An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop is located along a back portion of the retainer rest portion. The position of the rest stop can be adjusted to adjust the sensitivity of the system to earthquakes. The guide rails have retainer stops located at selected positions to keep the retainer from moving past. In one embodiment two retainers are provided and in another embodiment, a mesh is provided to contain items that would otherwise fall through.

Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors, including if the die has a defective component. An indication of the defective functional component identification is received. A determination is made if the defective functional component is one of a plurality of similar functional components that can provide the same functionality. The other similar components can be examined to determine if they are parallel components to the defective functional component. The defective functional component is disabled if it is one of the plurality of similar functional components and another component can handle the workflow that would otherwise be assigned to the defective component. Workflow is diverted from the disabled component to other similar functional components.

Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors. In one embodiment, manufacturing yields, compatibility characteristics, performance requirements, and system health (e.g., the number of components operating properly) are factored into changes to the operational characteristics of functional components. In one exemplary implementation, the changes to operational characteristics of a functional component are coordinated with changes to other functional components. Workflow scheduling and distribution is also adjusted based upon the changes to the operational characteristics of the functional components. For example, a functional component configuration controller changes the operational characteristics settings and provides an indication to a workflow distribution component.

Abstract: The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.

Abstract: The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.

Abstract: An earthquake-activated shelf security system has two guide rails attached to both sides of a shelf or pallet rack. At least one retainer is moveably constrained to move along the guide rails by a rotating loop located on each end of the retainer. The guide rail has a retainer rest portion and allows the retainer to rest in a prepared configuration without moving down the rail unless acted upon by a shaking event such as an earthquake. A movable backstop is located along a back portion of the retainer rest portion. The position of the rest stop can be adjusted to adjust the sensitivity of the system to earthquakes. The guide rails have retainer stops located at selected positions to keep the retainer from moving past. In one embodiment two retainers are provided and in another embodiment, a mesh is provided to contain items that would otherwise fall through.

Abstract: A method and circuit for generating a train of synthesized sync pulses in accordance with the Bresenham algorithm in response to an input clock having frequency Fi, such that the leading edges of the pulses occur at least nearly periodically, with time-averaged frequency at least nearly equal to (A/T)Fi, where A and T are integers, and such that the accumulated error, between the actual time interval between the first and last leading edges of Z consecutive ones of the pulses and the time ZT/(AFi), never exceeds 1/Fi. When Fi is equal to (T/A)Fo, where Fo is a predetermined output line frequency, an embodiment of the sync pulse generator includes an accumulator which stores a Count value, a comparator, and logic circuitry for generating the sync pulse train in response to a binary signal asserted by the comparator (and typically also control data that determines a configuration of the logic circuitry).

Abstract: A method and apparatus for producing output values corresponding to pixels of an input image. A coordinate translation circuit for is provided for performing coordinate translation from input pixel color components to corresponding texture coordinates. The texture coordinates collectively determine a texture address. The coordinate translation circuit also generates a set of interpolation factors in one embodiment used to resample around the point in texture space defined by the texture address. An interpolation circuit is coupled to the coordinate translation circuit to receive the texture address and the set of interpolation factors. The interpolation circuit uses the texture address and the set of interpolation factors to produce an output value. Typically, the output value represents a multidimensional lookup of the color components interpolated into multidimensional space.

Abstract: A method is used to access a sub-region of a two or more dimensional data region, in which said region is composed of a patchwork of individually addressable tiles. A hardware assisted mechanism is used to address, reformat, and composite data from each tile to produce a row-major subregion data stream to the consuming device. This method abstracts information about how the desired region is stored and addressed, so that further processing steps can process the data as a contiguous two or more dimensional space without regard to how the data is composited. This is particularly useful for doing image processing on graphics processing systems where source data is often stored in separately managed and addressed tiles.

Abstract: In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.

Abstract: In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.