Patents by Inventor Michael B. Solka
Michael B. Solka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11900124Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.Type: GrantFiled: January 3, 2023Date of Patent: February 13, 2024Assignee: Coherent Logix, IncorporatedInventors: Michael B Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Publication number: 20230276535Abstract: Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Inventors: Kevin A. Shelby, Michael B. Doerr, Michael B. Solka, Yama Yasha
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Patent number: 11683860Abstract: Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.Type: GrantFiled: November 4, 2021Date of Patent: June 20, 2023Assignee: Coherent Logix, IncorporatedInventors: Kevin A. Shelby, Michael B. Doerr, Michael B. Solka, Yama Yasha
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Publication number: 20230153117Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.Type: ApplicationFiled: January 3, 2023Publication date: May 18, 2023Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Patent number: 11544072Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.Type: GrantFiled: March 16, 2021Date of Patent: January 3, 2023Assignee: Coherent Logix, Inc.Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Patent number: 11483580Abstract: A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficiently and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.Type: GrantFiled: June 11, 2013Date of Patent: October 25, 2022Assignee: Coherent Logix, IncorporatedInventors: Michael W. Bruns, Michael B. Solka, Carl S. Dobbs, Martin A. Hunt, Michael B. Doerr, Tommy K. Eng
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Publication number: 20220061127Abstract: Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Inventors: Kevin A. Shelby, Michael B. Doerr, Michael B. Solka, Yama Yasha
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Patent number: 11212876Abstract: Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.Type: GrantFiled: November 27, 2019Date of Patent: December 28, 2021Assignee: Coherent Logix, IncorporatedInventors: Kevin A. Shelby, Michael B. Doerr, Michael B. Solka, Yama Yasha
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Publication number: 20210208895Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.Type: ApplicationFiled: March 16, 2021Publication date: July 8, 2021Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Patent number: 11016779Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.Type: GrantFiled: August 13, 2019Date of Patent: May 25, 2021Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Patent number: 10838787Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: GrantFiled: December 13, 2019Date of Patent: November 17, 2020Assignee: Coherent Logix, IncorporatedInventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Publication number: 20200302090Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: ApplicationFiled: June 10, 2020Publication date: September 24, 2020Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
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Patent number: 10685143Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: GrantFiled: June 4, 2018Date of Patent: June 16, 2020Assignee: COHERENT LOGIX, INCORPORATEDInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
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Publication number: 20200178355Abstract: Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.Type: ApplicationFiled: November 27, 2019Publication date: June 4, 2020Inventors: Kevin A. Shelby, Michael B. Doerr, Michael B. Solka, Yama Yasha
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Publication number: 20200117521Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Patent number: 10521285Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: GrantFiled: January 21, 2019Date of Patent: December 31, 2019Assignee: COHERENT LOGIX, INCORPORATEDInventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Publication number: 20190369990Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.Type: ApplicationFiled: August 13, 2019Publication date: December 5, 2019Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Publication number: 20190155666Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: ApplicationFiled: January 21, 2019Publication date: May 23, 2019Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Patent number: 10185608Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: GrantFiled: May 22, 2018Date of Patent: January 22, 2019Assignee: Coherent Logix, IncorporatedInventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Publication number: 20180276416Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: ApplicationFiled: June 4, 2018Publication date: September 27, 2018Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson