Abstract: Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is mapped to a first memory board and a second location is mapped to a second memory board. Data for a read operation is not replicated in cache. Other non-cache data that is critical and thus replicated includes metadata. Cache locations for data of read and write I/O operations are selected dynamically at the time the I/O operation is made from the same pool of cache locations.

Abstract: A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.

Abstract: A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.

Abstract: A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives.

Abstract: A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.

Abstract: A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.

Abstract: A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.

Abstract: A method and apparatus for hot-plugging circuit boards having lower voltage logic devices into a higher voltage backplane in a manner that minimizes overvoltage stress during system power-up, or during a lower voltage power failure. The method and apparatus ensures that the lower voltage device(s') power input reaches at least a nominal input level before any other inputs of the device are driven to a level greater than or equal to an expected input level. Dedicated output pins on lower voltage logic device(s) are configured to issue a control output signal for enabling higher voltage devices. Output enable terminals for the higher voltage parts, which are connected to respective control outputs from a lower voltage device, are normally in a disabled state as a function of pull-up or pull-down circuitry.

Abstract: An optimized memory refresh scheme controls and reduces instantaneous power consumption and power-related noise during DRAM refresh. In the optimized refresh implementation the DRAM is refreshed using a selectable overlap Column Address Select (CAS) before Row Address Select (RAS) refresh mode. A refresh interface between a host port and the memory system is over two bussed signals comprised of a Refresh Enable signal (Refresh.sub.-- Enable) and a Refresh Strobe pulse train (Refresh.sub.-- Strobe). Refresh.sub.-- Enable is issued by the host port to define a refresh operation. Refresh.sub.-- Strobe is a pulse train generated by the host port which is used as a clock for a sequential refresh sequencer. A refresh sequencer issues selectably timed column address refresh and row address refresh signals according to which the memory banks can all be selectably refreshed substantially in parallel, or with a predetermined selected level of overlap.

Abstract: A buffer memory includes at least one memory including a plurality of memory locations, and at least one write-control circuit. When data is written to one of the plurality of memory locations, the at least one write-control circuit causes at least one bit of validation information to be written to the at least one memory to indicate that the data written to the one of the plurality of memory locations is valid. In response to data being read from the one of the plurality of memory locations, the at least one write-control circuit causes the at least one bit of validation information to be overwritten to indicate that the data stored in the one of the plurality of memory locations is invalid.

Abstract: A modular memory array configuration uses a combinatorial decoding device (decoder), instead of straight buffering, to effect optimal delivery of control and address signals. Each port accessing memory on the array drives a single copy of address and control signals, plus bank select signals, over a shared interface to the decoder. Bank select controls the decoder which drives the address and control to only the accessed bank. Address and control signals to all banks but the accessed bank, are pulled up (inactive) with resistors on the memory array. For N banks, log2 N bank select bits are needed. The decoder device does not need to be clocked and therefore avoids problems associated with selecting between and providing asynchronous or redundant clocks for a multi-ported shared memory with ports independent of and asynchronous to one another.

Abstract: A storage apparatus including a memory; a first buffer into which data words are read from said memory; and a word selector receiving on a first input data words from the buffer and on a second input data words from another source, and producing on an output for storage back into the memory data words that are selected from the first and second inputs to the word selector.