Abstract: A method, system on a chip, and computer system for generating more robust keys which utilize data occupying relatively small die areas is disclosed. Embodiments provide a convenient and effective mechanism for generating a key for use in securing data on a portable electronic device, where the key is generated from repurposed data and a relatively small amount. A multi-stage encryption algorithm may be performed to generate the key, where the first stage may include encrypting the secure data, and the second stage may include encrypting the result of a logical operation on the encrypted secure data with a unique identifier of the portable electronic device. A secret key may be used as the encryption key for each stage. The result of the second encryption stage may include the generated key which may be used to perform subsequent operations on the portable electronic device.

Abstract: A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.

Abstract: A bridge associated with a broadcast aperture facilitates the transfer of rendering commands and data between a processor and multiple graphics devices. The bridge receives data written by the processor to the broadcast aperture and forwards it to multiple graphics devices, eliminating the need for the processor to perform duplicative(?) write operations. During system initialization, a broadcast aperture is allocated to the bridge in address space based on an aperture size value set using a system configuration utility and stored in system configuration memory. A graphics driver activates the broadcast aperture by sending unicast aperture parameters associated with the multiple graphics devices to the bridge via a bridge driver. Upon activating the broadcast aperture, multiple graphics devices can be operated in parallel to improve rendering performance. Parallel rendering techniques include split-frame, alternate frame, and combined split- and alternate frame rendering.

Abstract: Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.

Abstract: A computer graphics system for caching textures includes an L3 memory, an L2 cache, and an L1 cache for storing such textures and also includes a graphics accelerator (GA) for mapping these stored textures onto primitives for graphics display. The L3 memory, which has the largest capacity also has the slowest retrieval speed, while the L1 cache has the smallest capacity and the quickest retrieval speed. The textures are divided into a plurality of L2 texture blocks and each L2 texture block is subdivided into a plurality of L1 sub-blocks. During its rendering process, the GA searches the L1 cache for a particular L1 sub-block that is to be applied to a primitive. If such L1 sub-block is stored within the L1 cache, the GA will extract the desired texels (i.e., texture pixels) from the L1 sub-block and apply such texels to the primitive. If the L1 sub-block is not located in the L1 cache, the GA will search the L2 cache for the L1 sub-block.