Abstract: Compositions and methods for binding to a target sequence of interest are provided. The compositions find use in cleaving or modifying a target sequence of interest, visualization of a target sequence of interest, and modifying the expression of a sequence of interest. Compositions comprise RNA-guided nuclease (RGN) polypeptides, CRISPR RNAs, trans-activating CRISPR RNAs, guide RNAs, and nucleic acid molecules encoding the same. Vectors and host cells comprising the nucleic acid molecules are also provided. Further provided are RGN systems for binding a target sequence of interest, wherein the RGN system comprises an RNA-guided nuclease polypeptide and one or more guide RNAs.

Abstract: Compositions and methods for binding to a target sequence of interest are provided. The compositions find use in cleaving or modifying a target sequence of interest, visualization of a target sequence of interest, and modifying the expression of a sequence of interest. Compositions comprise RNA-guided nuclease polypeptides, CRISPR RNAs, trans-activating CRISPR RNAs, guide RNAs, and nucleic acid molecules encoding the same. Vectors and host cells comprising the nucleic acid molecules are also provided. Further provided are CRISPR systems for binding a target sequence of interest, wherein the CRISPR system comprises an RNA-guided nuclease polypeptide and one or more guide RNAs.

Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

Abstract: An integrated circuit memory device has a memory array and a non-volatile register for storing a stored signal. A bus is connected to the device for supplying an externally supplied signal to the device. A comparator compares the stored signal and the externally supplied signal and provides access to the memory array in response to the comparison.

Abstract: An integrated circuit 110 for concurrent flash memory. The circuit 110 has an uneven array architecture including a pair of arrays 112, 114 of a first size, and a pair of arrays 116, 118 of a second size. The arrays 112, 114, 116 and 118 are cooperatively linked in a manner which allows certain arrays to be read while other arrays are concurrently programmed or erased. The uneven array architecture of circuit 110 provides increased flexibility of bank size combinations for concurrent read and program/erase operation.

Abstract: An integrated circuit 110 for concurrent flash memory. The circuit 110 has an uneven array architecture including a pair of arrays 112, 114 of a first size, and a pair of arrays 116, 118 of a second size. The arrays 112, 114, 116 and 118 are cooperatively linked in a manner which allows certain arrays to be read while other arrays are concurrently programmed or erased. The uneven array architecture of circuit 110 provides increased flexibility of bank size combinations for concurrent read and program/erase operation.

Abstract: A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage V.sub.CC and high speed performance. This high speed performance is achieved by utilizing overerasure, a condition that was previously viewed as making a flash EEPROM cell inoperative. Specifically, the integrated circuit of this invention includes a flash EEPROM array wherein each flash EEPROM cell is overerased, and circuit means which erases, reads, and programs the overerased flash EEPROM cells. In each operation, the circuit means isolates all of the flash EEPROM cells in the array except a selected flash EEPROM cell so that leakage currents do not affect the flash EEPROM cell selected for the operation. The ability to perform the read operation on an overerased flash EEPROM cell is the mechanism that maintains the speed performance of the flash EEPROM array with the low power supply voltage.

Abstract: A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage V.sub.CC and high speed performance. This high speed performance is achieved by utilizing overerasure, a condition that was previously viewed as making a flash EEPROM cell inoperative, Specifically, the integrated circuit of this invention includes a flash EEPROM array wherein each flash EEPROM cell is overerased, and circuit means which erases, reads, and programs the overerased flash EEPROM cells. In each operation, the circuit means isolates all of the flash EEPROM cells in the array except a selected flash EEPROM cell so that leakage currents do not affect the flash EEPROM cell selected for the operation. The ability to perform the read operation on an overerased flash EEPROM cell is the mechanism that maintains the speed performance of the flash EEPROM array with the low power supply voltage.