Patents by Inventor Michael C. Parris
Michael C. Parris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9558808Abstract: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.Type: GrantFiled: March 28, 2016Date of Patent: January 31, 2017Assignee: Tessera, Inc.Inventor: Michael C. Parris
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Publication number: 20160211009Abstract: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.Type: ApplicationFiled: March 28, 2016Publication date: July 21, 2016Inventor: Michael C. PARRIS
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Patent number: 9299417Abstract: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.Type: GrantFiled: March 9, 2015Date of Patent: March 29, 2016Assignee: Tessera, Inc.Inventor: Michael C. Parris
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Patent number: 9158352Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.Type: GrantFiled: April 4, 2014Date of Patent: October 13, 2015Assignee: Tessera, Inc.Inventors: Richard Dewitt Crisp, Michael C. Parris, Mark Kroot
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Publication number: 20150287452Abstract: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.Type: ApplicationFiled: March 9, 2015Publication date: October 8, 2015Inventor: Michael C. Parris
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Patent number: 8976572Abstract: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.Type: GrantFiled: March 6, 2014Date of Patent: March 10, 2015Assignee: Tessera, Inc.Inventor: Michael C. Parris
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Publication number: 20140333371Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.Type: ApplicationFiled: April 4, 2014Publication date: November 13, 2014Applicant: Tessera, Inc.Inventors: Richard Dewitt Crisp, Michael C. Parris, Mark Kroot
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Publication number: 20140185402Abstract: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Applicant: TESSERA, INC.Inventor: Michael C. Parris
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Patent number: 8699263Abstract: In a method of erasing data, a wordline of the DRAM array is set active, and signals develop on bitlines according to flows of charge between memory cells coupled to the wordline and the respective bitlines. Sense amplifiers connected to the respective bitlines can remain off such that the sense amplifiers do not amplify the signals to storable signal levels. Thereafter, when the wordline is set inactive again, insufficient charge remains in the memory cells coupled to the wordline to represent data such that the data stored in memory cells coupled to the wordline are erased. These steps can be performed using each of the wordlines of a selected range of the DRAM array or all of the DRAM array so as to erase the data stored in the selected range or in all of the DRAM array.Type: GrantFiled: November 8, 2011Date of Patent: April 15, 2014Assignee: Tessera, Inc.Inventor: Michael C. Parris
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Patent number: 8692611Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.Type: GrantFiled: November 2, 2011Date of Patent: April 8, 2014Assignee: Tessera, Inc.Inventors: Richard Dewitt Crisp, Michael C. Parris, Mark Kroot
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Publication number: 20130051127Abstract: In a method of erasing data, a wordline of the DRAM array is set active, and signals develop on bitlines according to flows of charge between memory cells coupled to the wordline and the respective bitlines. Sense amplifiers connected to the respective bitlines can remain off such that the sense amplifiers do not amplify the signals to storable signal levels. Thereafter, when the wordline is set inactive again, insufficient charge remains in the memory cells coupled to the wordline to represent data such that the data stored in memory cells coupled to the wordline are erased. These steps can be performed using each of the wordlines of a selected range of the DRAM array or all of the DRAM array so as to erase the data stored in the selected range or in all of the DRAM array.Type: ApplicationFiled: November 8, 2011Publication date: February 28, 2013Applicant: TESSERA, INC.Inventor: Michael C. Parris
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Publication number: 20130043935Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.Type: ApplicationFiled: November 2, 2011Publication date: February 21, 2013Applicant: TESSERA, INC.Inventors: Richard Dewitt Crisp, Michael C. Parris, Mark Kroot
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Patent number: 8339882Abstract: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein.Type: GrantFiled: July 12, 2010Date of Patent: December 25, 2012Assignee: ProMOS Technologies Pte. Ltd.Inventors: Michael C. Parris, Kim C. Hardee
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Patent number: 8281219Abstract: An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time.Type: GrantFiled: August 16, 2007Date of Patent: October 2, 2012Assignee: Invensas CorporationInventors: Michael C. Parris, Oscar Frederick Jones, Jr.
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Publication number: 20120008444Abstract: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein.Type: ApplicationFiled: July 12, 2010Publication date: January 12, 2012Applicant: ProMOS Technologies PTE.LTD.Inventors: Michael C. Parris, Kim C. Hardee
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Publication number: 20120008445Abstract: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention provides both reference voltage (VSS) precharged sub arrays and VCC precharged sub arrays on the same DRAM memory either with or without the novel charge sharing or charge recycling circuitry between these two different sub arrays as disclosed herein.Type: ApplicationFiled: July 12, 2010Publication date: January 12, 2012Applicant: ProMOS Technologies PTE.LTD.Inventors: Michael C. Parris, Kim C. Hardee
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Patent number: 7916567Abstract: A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in terms of power, radiation hardness and speed and does not require intermediate supply voltage bitline precharge while allowing for 6F2 memory cell layouts.Type: GrantFiled: March 7, 2008Date of Patent: March 29, 2011Assignee: ProMOS Technologies Pte. LtdInventors: Michael C. Parris, Douglas B. Butler
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Patent number: 7649406Abstract: A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.Type: GrantFiled: September 13, 2007Date of Patent: January 19, 2010Assignees: United Memories, Inc., Sony CorporationInventors: Michael C. Parris, Kim C. Hardee
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Patent number: 7631233Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.Type: GrantFiled: October 7, 2007Date of Patent: December 8, 2009Assignees: United Memories, Inc., Sony CorporationInventors: Michael C. Parris, Oscar Frederick Jones, Jr.
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Patent number: RE44726Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.Type: GrantFiled: December 7, 2011Date of Patent: January 21, 2014Assignee: Invensas CorporationInventors: Michael C. Parris, Oscar Frederick Jones, Jr.